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Thu, 17 Oct 2024 11:53:19 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v4 06/26] cxl: add function for type2 cxl regs setup Date: Thu, 17 Oct 2024 17:52:05 +0100 Message-ID: <20241017165225.21206-7-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> References: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026368:EE_|IA1PR12MB6163:EE_ X-MS-Office365-Filtering-Correlation-Id: c547786d-829c-4d0d-40a6-08dceecc3539 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: 4B8P/TzHtrv3rTYkrRUIwblm2tUqxKPYlKIqjvg7GgASja0oyLMdDoOLSWmvZBt6xNu+m4/2TvPcbkCBHrgT4PuhJHXSQAGkZtlQqn86ozZqZ0sxfgDTnH4TyaFNLZALRkzlizHNRaXKA4XNgvX+9mh/6L5W5gvLwoRh7WlqL/q15VKDJxQGQR4kC6f0PqpnSDyftCIPtz97nLBS65qkfSfT7vBshlC4+EOVkct6hrOhPa6BeEWnrhyMVaQkCPHaMgtbUXailrwCsXYa9NJc9gaZ/E7ec1qak1UjXiOkAcL6Vx0KzQzsoHpMellXMu81tnbB7cW6RTWOxi/EHVuouIdCA2gb0Ae2++7Rf6EYV2U9R+ZuDXLcw4fQf27DPAyzILnuLS/4vW5chKgj8tN26I80h+btukzH9tegWpVnbaUQAFMSQdyfCwNGykOSNB899tU0ogjNdwXYUuGHToF7ejsMQaHEDsWTTt8I6vwqpHuc/2SLPQdhoH5SM02fAk4ZRgXSiqgGGUsKDhkMvNoETX85TO/Qi6vNZVjStIp6gras2IZrjYlu5H5YfQN4AR8NxfyCe3Zv/TFf/7KpewXnlsw0PBndnbcbPKgE7Scl08AYo+5BFTlFajWt1whe750SFnGa5S/ueDrIYOtpmSAeShFchB1rbOfAF406x8W8gWx33jaguCKA3FFpVw9Ir4pLsgiYq15s26O6TzB7xUNqU5dbKuS0cgc2Ww3gUkj0OGPRktJUNcff0lst6t/cycSN6MrlPXzyuihR9bzUl7KjHacsI2NTC31jaW+zdyKTTSsFfvbEAHyqX1PYvy9D0df7/66K7m2nM4xvIE0rKoU8BOpjvM6mhPMDdVbEDbtDJitdUtPQuOcOzPQj7lkz7hUvfAm6idhIsN8VRJKeSkV5nhyNGnBxVz4ycJOm4Edv7yitpWg/QheUi5xRWga8tNVHIJZVz6yr7LVShMdbfqkKHp2BK9dwDNxCKcQXZFyXpzraV1TnuX6J07mUihHOpNmKE/YBOkFzacaSaA0cttqzveCYagthTqYGg9Ut/MlzQbMc8HfOmntvie+s4j3CDWWlFSlVq+1ke06RvDZazd2lvA+kW8jFxS3Huabjiaz0fL8HC9Nm9ejXuFvKOLL7Lrzy5pZDctGTcRSn3p3raLaZeOi8XsoFWJaQ7DNYJiDrP9VZE+3eeW+BcX2HzfSLmkwymcKlujZUIh6yXajuMs3xVlimI8ZXJaZTV6QmWq7AJJs8IkpgPcnCIk7nFTRw69IJ+x08W5pMNoMTDgwLtG2blV7klK+zzZbQ+ZD8b/LeUE9vFdTVqkfF7CsKiI3uc6PhOdYc85MlJLY8fwXNH2cYOpbnzgl1H3mo14tDJ/i4PZ+tPQzfCoJCe9lyw8vXJ6I+qVHKI7GVXdYS0F0d5kcwcQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2024 16:53:21.2670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c547786d-829c-4d0d-40a6-08dceecc3539 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026368.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6163 From: Alejandro Lucero Create a new function for a type2 device initialising cxl_dev_state struct regarding cxl regs setup and mapping. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 47 +++++++++++++++++++++++++++++++++++++++++ include/linux/cxl/cxl.h | 2 ++ 2 files changed, 49 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 99acc258722d..f0f7e8bd4499 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1141,6 +1141,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call returning a non-zero value is not considered an error since + * these regs are not mandatory for Type2. If they do exist then mapping + * them should not fail. + */ + if (rc) + return 0; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps) { diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h index 78653fa4daa0..2f48ee591259 100644 --- a/include/linux/cxl/cxl.h +++ b/include/linux/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include +#include enum cxl_resource { CXL_RES_DPA, @@ -52,4 +53,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif