| Message ID | 20241017165225.21206-8-alejandro.lucero-palau@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: add Type2 device support | expand |
On 10/17/24 11:52 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Use cxl code for registers discovery and mapping. > > Validate capabilities found based on those registers against expected > capabilities. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > --- > drivers/net/ethernet/sfc/efx_cxl.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index fb3eef339b34..749aa97683fd 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_nic *efx) > { > #if IS_ENABLED(CONFIG_CXL_BUS) > struct pci_dev *pci_dev = efx->pci_dev; > + DECLARE_BITMAP(expected, CXL_MAX_CAPS); > + DECLARE_BITMAP(found, CXL_MAX_CAPS); > struct efx_cxl *cxl; > struct resource res; > u16 dvsec; > @@ -64,6 +66,23 @@ int efx_cxl_init(struct efx_nic *efx) > goto err2; > } > > + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); > + if (rc) { > + pci_err(pci_dev, "CXL accel setup regs failed"); > + goto err2; > + } > + > + bitmap_clear(expected, 0, BITS_PER_TYPE(unsigned long)); In some places you use BITS_PER_TYPE(unsigned long) for the size of the capabilities bitmap, while in others you use CXL_MAX_CAPS. Right now it isn't an issue since CXL_MAX_CAPS is way smaller than the size of an unsigned long, but I seem to remember Jonathan suggesting this for future proofing. So, I would suggest setting CXL_MAX_CAPS = BITS_PER_TYPE(unsigned long) and using CXL_MAX_CAPS everywhere (or just using CXL_MAX_CAPS as-is). Then, when/if there are more capabilities we can just increase what CXL_MAX_CAPS is set to. > + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); > + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); > + > + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { > + pci_err(pci_dev, > + "CXL device capabilities found(%08lx) not as expected(%08lx)", > + *found, *expected); > + goto err2; > + } > + > efx->cxl = cxl; > #endif >
On 10/17/24 22:49, Ben Cheatham wrote: > On 10/17/24 11:52 AM, alejandro.lucero-palau@amd.com wrote: >> From: Alejandro Lucero <alucerop@amd.com> >> >> Use cxl code for registers discovery and mapping. >> >> Validate capabilities found based on those registers against expected >> capabilities. >> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> --- >> drivers/net/ethernet/sfc/efx_cxl.c | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c >> index fb3eef339b34..749aa97683fd 100644 >> --- a/drivers/net/ethernet/sfc/efx_cxl.c >> +++ b/drivers/net/ethernet/sfc/efx_cxl.c >> @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_nic *efx) >> { >> #if IS_ENABLED(CONFIG_CXL_BUS) >> struct pci_dev *pci_dev = efx->pci_dev; >> + DECLARE_BITMAP(expected, CXL_MAX_CAPS); >> + DECLARE_BITMAP(found, CXL_MAX_CAPS); >> struct efx_cxl *cxl; >> struct resource res; >> u16 dvsec; >> @@ -64,6 +66,23 @@ int efx_cxl_init(struct efx_nic *efx) >> goto err2; >> } >> >> + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); >> + if (rc) { >> + pci_err(pci_dev, "CXL accel setup regs failed"); >> + goto err2; >> + } >> + >> + bitmap_clear(expected, 0, BITS_PER_TYPE(unsigned long)); > In some places you use BITS_PER_TYPE(unsigned long) for the size of the capabilities bitmap, > while in others you use CXL_MAX_CAPS. Right now it isn't an issue since CXL_MAX_CAPS is way > smaller than the size of an unsigned long, but I seem to remember Jonathan suggesting this > for future proofing. So, I would suggest setting CXL_MAX_CAPS = BITS_PER_TYPE(unsigned long) > and using CXL_MAX_CAPS everywhere (or just using CXL_MAX_CAPS as-is). Then, when/if there > are more capabilities we can just increase what CXL_MAX_CAPS is set to. The reason for using this BITS_PER_TYPE here is because with CXL_MAX_CAPS, as it is defined now, it would not clear those bits not covered by the current value. Defining CXL_MAX_CAPS as 32 in the enum would solce thais problem. I think that is cleaner than doing any masking depending on CXL_MAX_CAPS so I will do so in v5. Thanks >> + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); >> + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); >> + >> + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { >> + pci_err(pci_dev, >> + "CXL device capabilities found(%08lx) not as expected(%08lx)", >> + *found, *expected); >> + goto err2; >> + } >> + >> efx->cxl = cxl; >> #endif >>
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index fb3eef339b34..749aa97683fd 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_nic *efx) { #if IS_ENABLED(CONFIG_CXL_BUS) struct pci_dev *pci_dev = efx->pci_dev; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct efx_cxl *cxl; struct resource res; u16 dvsec; @@ -64,6 +66,23 @@ int efx_cxl_init(struct efx_nic *efx) goto err2; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err2; + } + + bitmap_clear(expected, 0, BITS_PER_TYPE(unsigned long)); + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); + + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { + pci_err(pci_dev, + "CXL device capabilities found(%08lx) not as expected(%08lx)", + *found, *expected); + goto err2; + } + efx->cxl = cxl; #endif