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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044FD.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.0 via Frontend Transport; Fri, 25 Oct 2024 21:03:33 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 16:03:32 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 02/14] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe port support Date: Fri, 25 Oct 2024 16:02:53 -0500 Message-ID: <20241025210305.27499-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241025210305.27499-1-terry.bowman@amd.com> References: <20241025210305.27499-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|IA0PR12MB7650:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b013aa2-16b4-4eed-e49b-08dcf5387cdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013|7416014|921020; X-Microsoft-Antispam-Message-Info: sC4UbLSEZ0+A2kbIcgZ+KGKhGncAi0E5Z5zIbLMTLOQKH33NhBmEJSDOhLihVT96uQesz6VQIXcoDsV3kip26m8YyjnSjQgnBZePSExNginrMg3KECe10cXu4XJNaI3WBuedg6A4nnt/3sJDgf3eOzMx0KYgYIJHYQH6wbQwvebA3c4p6/kzPFGssseh1mmUXPo+R9LYZLasZ/iHLZe9QeYsg4Ktw57XpTC6L0LS0gLDBSiSMwb9g8S/yQZ6JvNQjWi237FjaZ+8F2DVwNfPdE96k+a0B0j0NTXTFYQO73RXvUutLbPQ6JL0ILAwu0Q0E/K21tu0+W73rX06A70BRjq5yNnBI6eH7EF3qi3okLKn/5mY9zdjb9FcC3q6e3oK8R4PAxl0MfHYIfGEBUMao/8PC2NTV5NrkFZD5OS46/F9U9SDroo1QKoq3LIsVOB6stx7k/s/JujqTB7Ux9AUBHCUEXNLq0OlOuw2h/KH+RVE+7lQkPlmMKKYgWIyPDbArmsrgzo+DmlFEGoYqyEhbl2AjbHEbtfBehI7DlfZM0qwVhYLs539EBX57mDZWRtMs/8BbIgDtliKZXvaUtRhYzAWaXg8Osyg4uOCx0eWsbc84zDPFGQhhqc3WHHnbmrN/Omy9u83/JRWhBICR2hMAJvDGpGfZd0mqYMq6Xm3Yce12Yzu2E8JEQ0kby9BrMqwh377DtQjmX1s9TQeEx9QTedeK7q+9USpMlbSGuY4O6LQuMCk4or6MEdFwzTxqnm8qseUYdiVvceTZojXknpaRG+fiB4ZLW6NUhZzm4AHLoLawsX8Vdq+uJmd1h7/baMK/xjlthC2reaOLrdw5+OaNdjg2Q79HgQaZRk8sR7QCQEqWwNghCzjc7EX0Psb5m27VgczpYNIKjLCSric0pGwM0+SsmkSZNGlhUwopUguoc4P7h5cO7DdnLOxwuyXIGr2aQtj6jCkTB5y7O/irQKMiq0cS7k5oqAW0WGxi71kdbuU08Ks5Ce2Ool2wN/ru0XGe8O5ZhAy1x8kBPx5yqRCaz+POUI5k6dllunroDUpLsG4JAdSsNpM4oIoSnlc2Di5Sok4qyyM16ztTym9Rll34t7JXBRRMx+pJK4rSYajpBMF7rZXfSofPxyWZaxd5LC0xlogQBjlHFUSvyo4RzzHDFWt0Cdios9wBTP0EiOpweuPrKzcWJ/JZxCfq1E+naDMpXnkGPXvj0421rFds2bFXWVAwBMI74WXMMJ68aXdU5m50oa6AoijOAVylhSKoVEtArslnHoB4da8qKVX7vW/dmtdPKb3PenRvXgsmoIPl3hVVrcyZs0iiqtxumoDP+A4PICidm/XOYry4Afzq76k2OS1FdkYMLiUiLKzgacgEIsvnGkHs/lNC+DlxAxI/+p5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 21:03:33.9873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b013aa2-16b4-4eed-e49b-08dcf5387cdc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7650 The AER service driver already includes support for CXL restricted host (RCH) downstream port error handling. The current implementation is based on CXL1.1 using a root complex event collector. Rename function interfaces and parameters where necessary to include virtual hierarchy (VH) mode CXL PCIe port error handling alongside the RCH handling.[1] The CXL PCIe port error handling will be added in a future patch. Limit changes to renaming variable and function names. No functional changes are added. [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni --- drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 13b8586924ea..fe6edf26279e 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1029,7 +1029,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) return 0; } -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1052,30 +1052,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) return *handles_cxl; } -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); return handles_cxl; } -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif /** @@ -1113,7 +1113,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_rch_handle_error(dev, info); + cxl_handle_error(dev, info); pci_aer_handle_error(dev, info); pci_dev_put(dev); } @@ -1491,7 +1491,7 @@ static int aer_probe(struct pcie_device *dev) return status; } - cxl_rch_enable_rcec(port); + cxl_enable_internal_errors(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0;