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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8158.14 via Frontend Transport; Wed, 13 Nov 2024 21:56:50 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 13 Nov 2024 15:56:48 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 12/15] cxl/pci: Add error handler for CXL PCIe port RAS errors Date: Wed, 13 Nov 2024 15:54:26 -0600 Message-ID: <20241113215429.3177981-13-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241113215429.3177981-1-terry.bowman@amd.com> References: <20241113215429.3177981-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|MW3PR12MB4491:EE_ X-MS-Office365-Filtering-Correlation-Id: dfa7ca9e-c4ad-4a9b-32c9-08dd042e1410 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 21:56:50.4809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfa7ca9e-c4ad-4a9b-32c9-08dd042e1410 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4491 Introduce correctable and uncorrectable CXL PCIe port protocol error handlers. The handlers will be called with a 'struct pci_dev' parameter indicating the CXL port device requiring handling. The CXL PCIe port device's underlying 'struct device' will match the port device in the CXL topology. Use the PCIe port's device object to find the matching upstream, downstream, or root port in the CXL topology. The matching device will contain a reference to the RAS register block used to handle and log the error. Invoke the existing __cxl_handle_ras() or __cxl_handle_cor_ras() passing a reference to the RAS registers as a parameter. These functions will use the register reference to clear the device's RAS status. Future patches will assign the error handlers and add trace logging. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 64 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 62d29b5fd8f3..2c5cfc506f74 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -772,6 +772,70 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } +static int match_uport(struct device *dev, const void *data) +{ + struct device *uport_dev = (struct device *)data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port = to_cxl_port(dev); + + return port->uport_dev == uport_dev; +} + +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev) +{ + void __iomem *ras_base; + struct cxl_port *port; + + if (!pdev) + return NULL; + + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) { + struct cxl_dport *dport; + + port = find_cxl_port(&pdev->dev, &dport); + ras_base = dport ? dport->regs.ras : NULL; + if (port) + put_device(&port->dev); + return ras_base; + } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_UPSTREAM) { + struct device *port_dev; + + port_dev = bus_find_device(&cxl_bus_type, NULL, &pdev->dev, + match_uport); + if (!port_dev) + return NULL; + + port = to_cxl_port(port_dev); + ras_base = port ? port->uport_regs.ras : NULL; + put_device(port_dev); + return ras_base; + } + + return NULL; +} + +static void cxl_port_cor_error_detected(struct pci_dev *pdev) +{ + void __iomem *ras_base = cxl_pci_port_ras(pdev); + + __cxl_handle_cor_ras(&pdev->dev, ras_base); +} + +static bool cxl_port_error_detected(struct pci_dev *pdev) +{ + void __iomem *ras_base = cxl_pci_port_ras(pdev); + bool ue; + + ue = __cxl_handle_ras(&pdev->dev, ras_base); + + return ue; +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { /* uport may have more than 1 downstream EP. Check if already mapped. */