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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 21:57:14.0332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 721cafc5-3614-4431-1209-08dd042e220e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8842 pci_driver::cxl_err_handlers are not currently assigned handler callbacks. The handlers can't be set in the pci_driver static definition because the CXL PCIe port devices are bound to the portdrv driver which is not CXL driver aware. Add cxl_assign_port_error_handlers() in the cxl_core module. This function will assign the default handlers for a CXL PCIe port device. When the CXL port (cxl_port or cxl_dport) is destroyed the CXL PCIe port device's pci_driver::cxl_err_handlers must be set to NULL to prevent future use. Create cxl_clear_port_error_handlers() and register it to be called when the CXL port device (cxl_port or cxl_dport) is destroyed. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 794a601fdbf9..af2ff6936a09 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -844,8 +844,36 @@ static bool cxl_port_error_detected(struct pci_dev *pdev) return ue; } +static const struct cxl_error_handlers cxl_port_error_handlers = { + .error_detected = cxl_port_error_detected, + .cor_error_detected = cxl_port_cor_error_detected, +}; + +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) +{ + struct pci_driver *pdrv = pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler = &cxl_port_error_handlers; +} + +static void cxl_clear_port_error_handlers(void *data) +{ + struct pci_dev *pdev = data; + struct pci_driver *pdrv = pdev->driver; + + if (!pdrv) + return; + + pdrv->cxl_err_handler = NULL; +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { + struct pci_dev *pdev = to_pci_dev(port->uport_dev); + /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) return; @@ -856,6 +884,9 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(port->uport_dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL); @@ -868,6 +899,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { struct device *dport_dev = dport->dport_dev; struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); + struct pci_dev *pdev = to_pci_dev(dport_dev); if (dport->rch && host_bridge->native_aer) { cxl_dport_map_rch_aer(dport); @@ -884,6 +916,9 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(dport_dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL);