diff mbox series

[v2] cxl: avoid driver data for obtaining cxl_dev_state reference

Message ID 20241118163238.6723-1-alejandro.lucero-palau@amd.com
State New
Headers show
Series [v2] cxl: avoid driver data for obtaining cxl_dev_state reference | expand

Commit Message

Lucero Palau, Alejandro Nov. 18, 2024, 4:32 p.m. UTC 
From: Alejandro Lucero <alejandro.lucero-palau@amd.com>

CXL Type3 pci driver uses struct device driver_data for keeping
cxl_dev_state reference. Type1/2 drivers are not only about CXL so
this field should not be used when code requires cxl_dev_state to
work with and such a code used for Type2 support.

Change cxl_dvsec_rr_decode for passing cxl_dev_state as a parameter.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
---
 drivers/cxl/core/pci.c        | 6 +++---
 drivers/cxl/cxl.h             | 4 +++-
 drivers/cxl/port.c            | 2 +-
 tools/testing/cxl/test/mock.c | 6 +++---
 4 files changed, 10 insertions(+), 8 deletions(-)

Comments

kernel test robot Nov. 22, 2024, 1:46 a.m. UTC | #1 
Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on cxl/next]
[also build test ERROR on linus/master v6.12 next-20241121]
[cannot apply to cxl/pending]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/alejandro-lucero-palau-amd-com/cxl-avoid-driver-data-for-obtaining-cxl_dev_state-reference/20241121-141608
base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
patch link:    https://lore.kernel.org/r/20241118163238.6723-1-alejandro.lucero-palau%40amd.com
patch subject: [PATCH v2] cxl: avoid driver data for obtaining cxl_dev_state reference
config: mips-randconfig-r061-20241122 (https://download.01.org/0day-ci/archive/20241122/202411220917.CiqYJijn-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241122/202411220917.CiqYJijn-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411220917.CiqYJijn-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

   In file included from drivers/cxl/cxlmem.h:12,
                    from drivers/cxl/pci.c:15:
   drivers/cxl/cxl.h:830:24: error: storage class specified for parameter 'cxl_bus_type'
     830 | extern struct bus_type cxl_bus_type;
         |                        ^~~~~~~~~~~~
>> drivers/cxl/cxl.h:879:20: error: storage class specified for parameter 'is_cxl_pmem_region'
     879 | static inline bool is_cxl_pmem_region(struct device *dev)
         |                    ^~~~~~~~~~~~~~~~~~
>> drivers/cxl/cxl.h:879:20: warning: parameter 'is_cxl_pmem_region' declared 'inline'
>> drivers/cxl/cxl.h:880:1: warning: 'gnu_inline' attribute ignored [-Wattributes]
     880 | {
         | ^
>> drivers/cxl/cxl.h:879:20: error: 'no_instrument_function' attribute applies only to functions
     879 | static inline bool is_cxl_pmem_region(struct device *dev)
         | ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/cxl/cxl.h:880:1: error: expected ';', ',' or ')' before '{' token
     880 | {
         | ^
--
   In file included from drivers/perf/../cxl/cxlpci.h:6,
                    from drivers/perf/cxl_pmu.c:23:
   drivers/perf/../cxl/cxl.h:830:24: error: storage class specified for parameter 'cxl_bus_type'
     830 | extern struct bus_type cxl_bus_type;
         |                        ^~~~~~~~~~~~
>> drivers/perf/../cxl/cxl.h:879:20: error: storage class specified for parameter 'is_cxl_pmem_region'
     879 | static inline bool is_cxl_pmem_region(struct device *dev)
         |                    ^~~~~~~~~~~~~~~~~~
>> drivers/perf/../cxl/cxl.h:879:20: warning: parameter 'is_cxl_pmem_region' declared 'inline'
>> drivers/perf/../cxl/cxl.h:880:1: warning: 'gnu_inline' attribute ignored [-Wattributes]
     880 | {
         | ^
>> drivers/perf/../cxl/cxl.h:879:20: error: 'no_instrument_function' attribute applies only to functions
     879 | static inline bool is_cxl_pmem_region(struct device *dev)
         | ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/perf/../cxl/cxl.h:880:1: error: expected ';', ',' or ')' before '{' token
     880 | {
         | ^


vim +/is_cxl_pmem_region +879 drivers/cxl/cxl.h

779dd20cfb56c5 Ben Widawsky       2021-06-08  829  
b39cb1052a5cf4 Dan Williams       2021-02-16 @830  extern struct bus_type cxl_bus_type;
6af7139c979474 Dan Williams       2021-06-15  831  
6af7139c979474 Dan Williams       2021-06-15  832  struct cxl_driver {
6af7139c979474 Dan Williams       2021-06-15  833  	const char *name;
6af7139c979474 Dan Williams       2021-06-15  834  	int (*probe)(struct device *dev);
6af7139c979474 Dan Williams       2021-06-15  835  	void (*remove)(struct device *dev);
6af7139c979474 Dan Williams       2021-06-15  836  	struct device_driver drv;
6af7139c979474 Dan Williams       2021-06-15  837  	int id;
6af7139c979474 Dan Williams       2021-06-15  838  };
6af7139c979474 Dan Williams       2021-06-15  839  
d69d804845985c Greg Kroah-Hartman 2024-07-01  840  #define to_cxl_drv(__drv)	container_of_const(__drv, struct cxl_driver, drv)
6af7139c979474 Dan Williams       2021-06-15  841  
6af7139c979474 Dan Williams       2021-06-15  842  int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
6af7139c979474 Dan Williams       2021-06-15  843  			  const char *modname);
6af7139c979474 Dan Williams       2021-06-15  844  #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
6af7139c979474 Dan Williams       2021-06-15  845  void cxl_driver_unregister(struct cxl_driver *cxl_drv);
6af7139c979474 Dan Williams       2021-06-15  846  
c57cae78bfa6a8 Ben Widawsky       2022-01-23  847  #define module_cxl_driver(__cxl_driver) \
c57cae78bfa6a8 Ben Widawsky       2022-01-23  848  	module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
c57cae78bfa6a8 Ben Widawsky       2022-01-23  849  
8fdcb1704f61a8 Dan Williams       2021-06-15  850  #define CXL_DEVICE_NVDIMM_BRIDGE	1
21083f51521fb0 Dan Williams       2021-06-15  851  #define CXL_DEVICE_NVDIMM		2
54cdbf845cf719 Ben Widawsky       2022-02-01  852  #define CXL_DEVICE_PORT			3
54cdbf845cf719 Ben Widawsky       2022-02-01  853  #define CXL_DEVICE_ROOT			4
8dd2bc0f8e02d3 Ben Widawsky       2022-02-04  854  #define CXL_DEVICE_MEMORY_EXPANDER	5
8d48817df6ac20 Dan Williams       2021-06-15  855  #define CXL_DEVICE_REGION		6
04ad63f086d1a9 Dan Williams       2022-01-11  856  #define CXL_DEVICE_PMEM_REGION		7
09d09e04d2fcf8 Dan Williams       2023-02-10  857  #define CXL_DEVICE_DAX_REGION		8
1ad3f701c39999 Jonathan Cameron   2023-05-26  858  #define CXL_DEVICE_PMU			9
8fdcb1704f61a8 Dan Williams       2021-06-15  859  
6af7139c979474 Dan Williams       2021-06-15  860  #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
6af7139c979474 Dan Williams       2021-06-15  861  #define CXL_MODALIAS_FMT "cxl:t%d"
6af7139c979474 Dan Williams       2021-06-15  862  
8fdcb1704f61a8 Dan Williams       2021-06-15  863  struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
8fdcb1704f61a8 Dan Williams       2021-06-15  864  struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
8fdcb1704f61a8 Dan Williams       2021-06-15  865  						     struct cxl_port *port);
21083f51521fb0 Dan Williams       2021-06-15  866  struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
21083f51521fb0 Dan Williams       2021-06-15  867  bool is_cxl_nvdimm(struct device *dev);
53989fad1286e6 Dan Williams       2021-11-11  868  bool is_cxl_nvdimm_bridge(struct device *dev);
84ec985944ef34 Li Ming            2024-06-12  869  int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd);
84ec985944ef34 Li Ming            2024-06-12  870  struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
04ad63f086d1a9 Dan Williams       2022-01-11  871  
04ad63f086d1a9 Dan Williams       2022-01-11  872  #ifdef CONFIG_CXL_REGION
04ad63f086d1a9 Dan Williams       2022-01-11  873  bool is_cxl_pmem_region(struct device *dev);
04ad63f086d1a9 Dan Williams       2022-01-11  874  struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
a32320b71f085f Dan Williams       2023-02-10  875  int cxl_add_to_region(struct cxl_port *root,
a32320b71f085f Dan Williams       2023-02-10  876  		      struct cxl_endpoint_decoder *cxled);
09d09e04d2fcf8 Dan Williams       2023-02-10  877  struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
04ad63f086d1a9 Dan Williams       2022-01-11  878  #else
04ad63f086d1a9 Dan Williams       2022-01-11 @879  static inline bool is_cxl_pmem_region(struct device *dev)
04ad63f086d1a9 Dan Williams       2022-01-11 @880  {
04ad63f086d1a9 Dan Williams       2022-01-11  881  	return false;
04ad63f086d1a9 Dan Williams       2022-01-11  882  }
04ad63f086d1a9 Dan Williams       2022-01-11  883  static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
04ad63f086d1a9 Dan Williams       2022-01-11  884  {
04ad63f086d1a9 Dan Williams       2022-01-11  885  	return NULL;
04ad63f086d1a9 Dan Williams       2022-01-11  886  }
a32320b71f085f Dan Williams       2023-02-10  887  static inline int cxl_add_to_region(struct cxl_port *root,
a32320b71f085f Dan Williams       2023-02-10  888  				    struct cxl_endpoint_decoder *cxled)
a32320b71f085f Dan Williams       2023-02-10  889  {
a32320b71f085f Dan Williams       2023-02-10  890  	return 0;
a32320b71f085f Dan Williams       2023-02-10  891  }
09d09e04d2fcf8 Dan Williams       2023-02-10  892  static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
09d09e04d2fcf8 Dan Williams       2023-02-10  893  {
09d09e04d2fcf8 Dan Williams       2023-02-10  894  	return NULL;
09d09e04d2fcf8 Dan Williams       2023-02-10  895  }
04ad63f086d1a9 Dan Williams       2022-01-11  896  #endif
67dcdd4d3b832a Dan Williams       2021-09-14  897
Alejandro Lucero Palau Nov. 22, 2024, 8:45 a.m. UTC | #2 
Hi all,


In v2 I fixed other problems reported by the robot which were directly 
related to the patch changes.

However, I can not see a link between this one reported now and the 
patch. It is a mips build ...

What should I do here?


On 11/22/24 01:46, kernel test robot wrote:
> Hi,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on cxl/next]
> [also build test ERROR on linus/master v6.12 next-20241121]
> [cannot apply to cxl/pending]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url:    https://github.com/intel-lab-lkp/linux/commits/alejandro-lucero-palau-amd-com/cxl-avoid-driver-data-for-obtaining-cxl_dev_state-reference/20241121-141608
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
> patch link:    https://lore.kernel.org/r/20241118163238.6723-1-alejandro.lucero-palau%40amd.com
> patch subject: [PATCH v2] cxl: avoid driver data for obtaining cxl_dev_state reference
> config: mips-randconfig-r061-20241122 (https://download.01.org/0day-ci/archive/20241122/202411220917.CiqYJijn-lkp@intel.com/config)
> compiler: mips-linux-gcc (GCC) 14.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241122/202411220917.CiqYJijn-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202411220917.CiqYJijn-lkp@intel.com/
>
> All error/warnings (new ones prefixed by >>):
>
>     In file included from drivers/cxl/cxlmem.h:12,
>                      from drivers/cxl/pci.c:15:
>     drivers/cxl/cxl.h:830:24: error: storage class specified for parameter 'cxl_bus_type'
>       830 | extern struct bus_type cxl_bus_type;
>           |                        ^~~~~~~~~~~~
>>> drivers/cxl/cxl.h:879:20: error: storage class specified for parameter 'is_cxl_pmem_region'
>       879 | static inline bool is_cxl_pmem_region(struct device *dev)
>           |                    ^~~~~~~~~~~~~~~~~~
>>> drivers/cxl/cxl.h:879:20: warning: parameter 'is_cxl_pmem_region' declared 'inline'
>>> drivers/cxl/cxl.h:880:1: warning: 'gnu_inline' attribute ignored [-Wattributes]
>       880 | {
>           | ^
>>> drivers/cxl/cxl.h:879:20: error: 'no_instrument_function' attribute applies only to functions
>       879 | static inline bool is_cxl_pmem_region(struct device *dev)
>           | ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/cxl/cxl.h:880:1: error: expected ';', ',' or ')' before '{' token
>       880 | {
>           | ^
> --
>     In file included from drivers/perf/../cxl/cxlpci.h:6,
>                      from drivers/perf/cxl_pmu.c:23:
>     drivers/perf/../cxl/cxl.h:830:24: error: storage class specified for parameter 'cxl_bus_type'
>       830 | extern struct bus_type cxl_bus_type;
>           |                        ^~~~~~~~~~~~
>>> drivers/perf/../cxl/cxl.h:879:20: error: storage class specified for parameter 'is_cxl_pmem_region'
>       879 | static inline bool is_cxl_pmem_region(struct device *dev)
>           |                    ^~~~~~~~~~~~~~~~~~
>>> drivers/perf/../cxl/cxl.h:879:20: warning: parameter 'is_cxl_pmem_region' declared 'inline'
>>> drivers/perf/../cxl/cxl.h:880:1: warning: 'gnu_inline' attribute ignored [-Wattributes]
>       880 | {
>           | ^
>>> drivers/perf/../cxl/cxl.h:879:20: error: 'no_instrument_function' attribute applies only to functions
>       879 | static inline bool is_cxl_pmem_region(struct device *dev)
>           | ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/perf/../cxl/cxl.h:880:1: error: expected ';', ',' or ')' before '{' token
>       880 | {
>           | ^
>
>
> vim +/is_cxl_pmem_region +879 drivers/cxl/cxl.h
>
> 779dd20cfb56c5 Ben Widawsky       2021-06-08  829
> b39cb1052a5cf4 Dan Williams       2021-02-16 @830  extern struct bus_type cxl_bus_type;
> 6af7139c979474 Dan Williams       2021-06-15  831
> 6af7139c979474 Dan Williams       2021-06-15  832  struct cxl_driver {
> 6af7139c979474 Dan Williams       2021-06-15  833  	const char *name;
> 6af7139c979474 Dan Williams       2021-06-15  834  	int (*probe)(struct device *dev);
> 6af7139c979474 Dan Williams       2021-06-15  835  	void (*remove)(struct device *dev);
> 6af7139c979474 Dan Williams       2021-06-15  836  	struct device_driver drv;
> 6af7139c979474 Dan Williams       2021-06-15  837  	int id;
> 6af7139c979474 Dan Williams       2021-06-15  838  };
> 6af7139c979474 Dan Williams       2021-06-15  839
> d69d804845985c Greg Kroah-Hartman 2024-07-01  840  #define to_cxl_drv(__drv)	container_of_const(__drv, struct cxl_driver, drv)
> 6af7139c979474 Dan Williams       2021-06-15  841
> 6af7139c979474 Dan Williams       2021-06-15  842  int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
> 6af7139c979474 Dan Williams       2021-06-15  843  			  const char *modname);
> 6af7139c979474 Dan Williams       2021-06-15  844  #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
> 6af7139c979474 Dan Williams       2021-06-15  845  void cxl_driver_unregister(struct cxl_driver *cxl_drv);
> 6af7139c979474 Dan Williams       2021-06-15  846
> c57cae78bfa6a8 Ben Widawsky       2022-01-23  847  #define module_cxl_driver(__cxl_driver) \
> c57cae78bfa6a8 Ben Widawsky       2022-01-23  848  	module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
> c57cae78bfa6a8 Ben Widawsky       2022-01-23  849
> 8fdcb1704f61a8 Dan Williams       2021-06-15  850  #define CXL_DEVICE_NVDIMM_BRIDGE	1
> 21083f51521fb0 Dan Williams       2021-06-15  851  #define CXL_DEVICE_NVDIMM		2
> 54cdbf845cf719 Ben Widawsky       2022-02-01  852  #define CXL_DEVICE_PORT			3
> 54cdbf845cf719 Ben Widawsky       2022-02-01  853  #define CXL_DEVICE_ROOT			4
> 8dd2bc0f8e02d3 Ben Widawsky       2022-02-04  854  #define CXL_DEVICE_MEMORY_EXPANDER	5
> 8d48817df6ac20 Dan Williams       2021-06-15  855  #define CXL_DEVICE_REGION		6
> 04ad63f086d1a9 Dan Williams       2022-01-11  856  #define CXL_DEVICE_PMEM_REGION		7
> 09d09e04d2fcf8 Dan Williams       2023-02-10  857  #define CXL_DEVICE_DAX_REGION		8
> 1ad3f701c39999 Jonathan Cameron   2023-05-26  858  #define CXL_DEVICE_PMU			9
> 8fdcb1704f61a8 Dan Williams       2021-06-15  859
> 6af7139c979474 Dan Williams       2021-06-15  860  #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
> 6af7139c979474 Dan Williams       2021-06-15  861  #define CXL_MODALIAS_FMT "cxl:t%d"
> 6af7139c979474 Dan Williams       2021-06-15  862
> 8fdcb1704f61a8 Dan Williams       2021-06-15  863  struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
> 8fdcb1704f61a8 Dan Williams       2021-06-15  864  struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
> 8fdcb1704f61a8 Dan Williams       2021-06-15  865  						     struct cxl_port *port);
> 21083f51521fb0 Dan Williams       2021-06-15  866  struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
> 21083f51521fb0 Dan Williams       2021-06-15  867  bool is_cxl_nvdimm(struct device *dev);
> 53989fad1286e6 Dan Williams       2021-11-11  868  bool is_cxl_nvdimm_bridge(struct device *dev);
> 84ec985944ef34 Li Ming            2024-06-12  869  int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd);
> 84ec985944ef34 Li Ming            2024-06-12  870  struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
> 04ad63f086d1a9 Dan Williams       2022-01-11  871
> 04ad63f086d1a9 Dan Williams       2022-01-11  872  #ifdef CONFIG_CXL_REGION
> 04ad63f086d1a9 Dan Williams       2022-01-11  873  bool is_cxl_pmem_region(struct device *dev);
> 04ad63f086d1a9 Dan Williams       2022-01-11  874  struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
> a32320b71f085f Dan Williams       2023-02-10  875  int cxl_add_to_region(struct cxl_port *root,
> a32320b71f085f Dan Williams       2023-02-10  876  		      struct cxl_endpoint_decoder *cxled);
> 09d09e04d2fcf8 Dan Williams       2023-02-10  877  struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
> 04ad63f086d1a9 Dan Williams       2022-01-11  878  #else
> 04ad63f086d1a9 Dan Williams       2022-01-11 @879  static inline bool is_cxl_pmem_region(struct device *dev)
> 04ad63f086d1a9 Dan Williams       2022-01-11 @880  {
> 04ad63f086d1a9 Dan Williams       2022-01-11  881  	return false;
> 04ad63f086d1a9 Dan Williams       2022-01-11  882  }
> 04ad63f086d1a9 Dan Williams       2022-01-11  883  static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
> 04ad63f086d1a9 Dan Williams       2022-01-11  884  {
> 04ad63f086d1a9 Dan Williams       2022-01-11  885  	return NULL;
> 04ad63f086d1a9 Dan Williams       2022-01-11  886  }
> a32320b71f085f Dan Williams       2023-02-10  887  static inline int cxl_add_to_region(struct cxl_port *root,
> a32320b71f085f Dan Williams       2023-02-10  888  				    struct cxl_endpoint_decoder *cxled)
> a32320b71f085f Dan Williams       2023-02-10  889  {
> a32320b71f085f Dan Williams       2023-02-10  890  	return 0;
> a32320b71f085f Dan Williams       2023-02-10  891  }
> 09d09e04d2fcf8 Dan Williams       2023-02-10  892  static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
> 09d09e04d2fcf8 Dan Williams       2023-02-10  893  {
> 09d09e04d2fcf8 Dan Williams       2023-02-10  894  	return NULL;
> 09d09e04d2fcf8 Dan Williams       2023-02-10  895  }
> 04ad63f086d1a9 Dan Williams       2022-01-11  896  #endif
> 67dcdd4d3b832a Dan Williams       2021-09-14  897
>
diff mbox series

Patch

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 5b46bc46aaa9..420e4be85a1f 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -291,11 +291,11 @@  static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm)
 	return devm_add_action_or_reset(host, disable_hdm, cxlhdm);
 }
 
-int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
+int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
 			struct cxl_endpoint_dvsec_info *info)
 {
-	struct pci_dev *pdev = to_pci_dev(dev);
-	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
+	struct device *dev = cxlds->dev;
 	int hdm_count, rc, i, ranges = 0;
 	int d = cxlds->cxl_dvsec;
 	u16 cap, ctrl;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 5406e3ab3d4a..a2be05fd7aa2 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -812,7 +812,9 @@  struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
 				struct cxl_endpoint_dvsec_info *info);
 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
-int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
+struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
+struct cxl_dev_state;
+int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
 			struct cxl_endpoint_dvsec_info *info);
 
 bool is_cxl_region(struct device *dev);
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 9dc394295e1f..acf2ac70f343 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -98,7 +98,7 @@  static int cxl_endpoint_port_probe(struct cxl_port *port)
 	struct cxl_port *root;
 	int rc;
 
-	rc = cxl_dvsec_rr_decode(cxlds->dev, port, &info);
+	rc = cxl_dvsec_rr_decode(cxlds, &info);
 	if (rc < 0)
 		return rc;
 
diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
index f4ce96cc11d4..4f82716cfc16 100644
--- a/tools/testing/cxl/test/mock.c
+++ b/tools/testing/cxl/test/mock.c
@@ -228,16 +228,16 @@  int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
 }
 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
 
-int __wrap_cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
+int __wrap_cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
 			       struct cxl_endpoint_dvsec_info *info)
 {
 	int rc = 0, index;
 	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
 
-	if (ops && ops->is_mock_dev(dev))
+	if (ops && ops->is_mock_dev(cxlds->dev))
 		rc = 0;
 	else
-		rc = cxl_dvsec_rr_decode(dev, port, info);
+		rc = cxl_dvsec_rr_decode(cxlds, info);
 	put_cxl_mock_ops(index);
 
 	return rc;