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Mon, 9 Dec 2024 12:54:42 -0600 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v7 04/28] cxl/pci: add check for validating capabilities Date: Mon, 9 Dec 2024 18:54:05 +0000 Message-ID: <20241209185429.54054-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241209185429.54054-1-alejandro.lucero-palau@amd.com> References: <20241209185429.54054-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBF:EE_|CH0PR12MB8532:EE_ X-MS-Office365-Filtering-Correlation-Id: cdd1fad1-2b9e-430c-8220-08dd1882f262 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: Lreg3FO1P0gTYSoUeXuFBlF4y1+6krApV+4PrWgf9VfYEoyrOyxoMfNeIrXazxyBs1SL301g4k/k81npG1BGlC3dVuqN8Nbx2dWBI56uY1J9RuasoJJTgBZBcQztgpqRHIy1l+UbsRp+q2d+2kBl68SGL+vvBwYdC7On/PrzQ7DiW6RGYBIZ+4mxYUM4DIK8scA4ClnCkC99Ed8Lje77k5TqL8QJjwzOxCU4ZIDUo4zlguPFnzjHRBc9aGn3bXaBl10fUg5XoRAqCEBhSkvnErRl4s5GAxTwJ+4Ffff8txh4C7TW6AL0IANoEGzENa+o13T6BRiiVlvAPLlkBpavsQ8suGcbqcalbve7fnQdwjOKFLOq9barDlXjmXWY9HjpEisgVMchNa4jOMFothW1lNbXaLw6o5SKUi3CYl8J1ULfbbfOkpeNtbSzo76iqynTv6eQetnMwlDdhW+G5rzvUYkvZU6ImxsjQwKbwhoO+1v+aN3/rVfl+tmohZSjBE7yqwEJvwRMQZM3/bGVuEbfSjHUsqNlYAC0GWThN39lfx4G/jzNZ1skQyakkuNcZ368A3B4B7r+mi2EAAFQhrT15Pv4ngjWP08JJmfajjgsrHoscioD3farUTXK0nBbETApNslHWpKKygFsR0eunp9pNGQh+s+x83ixzYfVfZsEqTGGjvEUaYNnGxcunuk0VfxQnl0V5ugeQkVrwpsVSFErviHKBkDoLlD4+1DV5wH4A765Xslyxd0TFN6mADIoRmWTwGbGA2MIM+WI2MovYVcz7Q3MiPdNyav3MHzuDS8ocEfH6Yl9glixfzTG8jYch48rd3Za2qZHZNIga2v3PXg5QhrHJrGQGPB+w+vWTA6WQukX7FvyirAbubeUH1wClPR37VW3iBLgt8JYxn8KzN4g1bRWNIwPiG5UpLzBF0zYVzBBNzE4e2kDsmQ5gux4Qmst7J1JSltjuQY+IWz5aAuWf2ZDd3BbiYIH/t3NOCThxdV6lalyA/ArF8003aHRE8+e91rfTZ5adI1odmj9NqcduZDDAFmtQ0lfgRq8hwEJ+HJ6MU86oby2Hg9YSuALF2ELXW1tQWoVs2jq9WK0xRUxMJjXnoseoBXKi9+ygptN+ysN1b/Qu/cVpjIpTOcZY4U4AyOUlhNzG712DPI4HswRHw9XlnNhIBkZ8BTI5bJm77FBfkw1nqNhny068U49IQ8Rv5uiiEDaXI7bXZtklUbWidqLTLbA9xgOayn9Rqnf+Y1wlNSFM3DvltNHnI0vlcLvzUw1qxKnzVlxg59m/UmMRr3l4hVIOWNrcb0a3BpBJo1+uFT1SHUSDmEsp6wgQqwxQN6rBsXGmM19V1RLIf3A6HbYMG7je2x0CCuYqazOPTMFmKi9nOI2wPwwYhCE+L2mPNl7aLr+t1vkOIqnvATZQmSRvnUYOjiXwwZI6TFxSHkb+KnBxHaouVOf74DWbq6yQDPX6EuJBnittar1U4WscQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:54:44.7210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdd1fad1-2b9e-430c-8220-08dd1882f262 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8532 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization and allow those mandatory/expected capabilities to be a subset of the capabilities found. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero Reviewed-by: Zhi Wang --- drivers/cxl/core/pci.c | 16 ++++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 24 ++++++++++++++++++++++++ include/cxl/cxl.h | 3 +++ 4 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c07651cd8f3d..bc098b2ce55d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1055,3 +1056,18 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) return 0; } + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, + unsigned long *current_caps) +{ + + if (current_caps) + bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS); + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%08lx vs expected caps 0x%08lx\n", + *cxlds->capabilities, *expected_caps); + + /* Checking a minimum of mandatory/expected capabilities */ + return bitmap_subset(expected_caps, cxlds->capabilities, CXL_MAX_CAPS); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, "CXL"); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index ac3a27c6e442..deaf18be896d 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -446,15 +446,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index dbc1cd9bec09..1fcc53df1217 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -903,6 +903,8 @@ __ATTRIBUTE_GROUPS(cxl_rcd); static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct cxl_memdev_state *mds; struct cxl_dev_state *cxlds; struct cxl_register_map map; @@ -964,6 +966,28 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + bitmap_clear(expected, 0, CXL_MAX_CAPS); + + /* + * These are the mandatory capabilities for a Type3 device. + * Only checking capabilities used by current Linux drivers. + */ + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + bitmap_set(expected, CXL_DEV_CAP_MAILBOX_PRIMARY, 1); + bitmap_set(expected, CXL_DEV_CAP_MEMDEV, 1); + + /* + * Checking mandatory caps are there as, at least, a subset of those + * found. + */ + if (!cxl_pci_check_caps(cxlds, expected, found)) { + dev_err(&pdev->dev, + "Expected mandatory capabilities not found: (%08lx - %08lx)\n", + *expected, *found); + return -ENXIO; + } + rc = cxl_pci_type3_init_mailbox(cxlds); if (rc) return rc; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index f656fcd4945f..05f06bfd2c29 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -37,4 +37,7 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, + unsigned long *expected_caps, + unsigned long *current_caps); #endif