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Mon, 16 Dec 2024 10:10:56 -0600 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v8 04/27] cxl/pci: add check for validating capabilities Date: Mon, 16 Dec 2024 16:10:19 +0000 Message-ID: <20241216161042.42108-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> References: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD75:EE_|BY5PR12MB4147:EE_ X-MS-Office365-Filtering-Correlation-Id: b602c374-1a18-44c4-77c3-08dd1dec3a69 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: yGgQfYYpw5qY7p9uAyN2IZHHKh95dgS3vt3zK4GMepejY5id40/SzMixqtCQXYF7+2BB337JPGo31ky6Sx7ehTOhXQGSpDbh3Dr4qjw9KhfXCB9DSYxnqBOY0QvcLUF1zOp0P2lvjUjOG/qJj294lgbsvd6lhL9ai/84Ct/yl81Df5KTFGw/vb6zYFyOI/RxB+VI/yj8QwPBaU0eJoBZozvLJzu+7bDXPi33kS78tI/3gUSFh8iQhbkPXXl6rKnX5alynOZsuNxPPxGfQT99LoFCkeXS1hwQQZkqcifpa5/VP/GMK1J69HG9MPFVFUzyGTYBudEwEK60EOr0ypnfIbxoO/Wt+5wI2IdaZ/e+GEzPvB7Y+z7qSwDcelQQEm6nBLvUydqL32zwCLlJk+CGRbnpbUhGv+ZIA2Il+K7OtMaUnKX+eDw9Tw5mjIur9za+iG5HoPF75KENI8xUSYjnN8xM9n2LLhP2TE9qJIgxjT8o1NLhIJJTiYkxekPNDe9D5lVGrcybolKj3AqXGccA0fnMVF/uyssQkHnM0KhsoQYGb9ZudmpGYAKqPYM6kutLaOsDVclqWe22BBxwuiAC1noLqxehqfCMHvdY64hb7AG+i0PQ0g/oD/YSrLwxoDJqLgatx7zH2r9lsELvYE5Af3tD2AJne0h0ccl83Yhwj6PWj1J/2e5G2pw+YxqUgnDoPNL2Rb+vxlSzGhKhFMdR6lnuUlr5XPKSMvC8SZah5yq8+GUmUdNVpC3uGOXOqeCtB49ExhYlMLgsAhwL4O5S1lss48oN4uxlA+uaMwQeu7Scn6PCiwdJGp9c9rUpdb0DSLVHTXJY9Sr7HnY6PscSM/hYZX8QuEeZEp3oU4TWyxQeqRI9VoAaUXNu3aH4iCodWRaolQoeObYGZ5ARK8+vH+aPss+a0HcAOpF13y4BmbxK3YMRrOIewD1WegSE32Jjt5Gn4AH1hq9u+FmmxqA0i/ikWZ0QIA0YSJm2/Y0Z6yW9JtIqCrLrwvX+Z6x/Up8qtX3RN381T/njSlWZCCtaufWzGEUXbltBUofbL5AHrKAkfaMdZX/r1503ESiiHxZYAFEfi5foNBiIULm/2hEfkLXeMvn8ITKbAeoq3bMYdyQhvzApSd2ClspYDp5rdFT7MT3Xo3/5omPr6l/8mdXa3zfFCxCR08w1AeVkSbNTKZjhAXvWjR5sOTxCtyN+dQMqBl5ewOU8B7gQd0X4xEPzOry0y3O4RP6tq5msqiZxixLyv5B6Hnx7b4s5DaUfcqhWILrNRiafr+Yd00tNmgWLotBiXLycH3klG6CmvGaBnBpbzkZ5/LZC/3ppQ/FgRJ2ErZyUdGxptU8YMO5BRetRlK6cNmje0mBNo+Wr/rm4GwVOKQTQS0TF7xNPEIk8FKDbmj31OfrQUgNFa2npki0Yk1u4nv+DrHyw6AutJqEtyLCPV0nJS1pJ/JS/KWd3a3hMxeDjD0hX51YOqGViN2TgyVo20UJYbWKkQoGA8sUdk7g= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Dec 2024 16:10:58.5175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b602c374-1a18-44c4-77c3-08dd1dec3a69 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD75.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4147 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization and allow those mandatory/expected capabilities to be a subset of the capabilities found. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero Reviewed-by: Zhi Wang --- drivers/cxl/core/pci.c | 16 ++++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 24 ++++++++++++++++++++++++ include/cxl/cxl.h | 3 +++ 4 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c07651cd8f3d..bc098b2ce55d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1055,3 +1056,18 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) return 0; } + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, + unsigned long *current_caps) +{ + + if (current_caps) + bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS); + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%08lx vs expected caps 0x%08lx\n", + *cxlds->capabilities, *expected_caps); + + /* Checking a minimum of mandatory/expected capabilities */ + return bitmap_subset(expected_caps, cxlds->capabilities, CXL_MAX_CAPS); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, "CXL"); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index ac3a27c6e442..deaf18be896d 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -446,15 +446,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index dbc1cd9bec09..1fcc53df1217 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -903,6 +903,8 @@ __ATTRIBUTE_GROUPS(cxl_rcd); static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct cxl_memdev_state *mds; struct cxl_dev_state *cxlds; struct cxl_register_map map; @@ -964,6 +966,28 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + bitmap_clear(expected, 0, CXL_MAX_CAPS); + + /* + * These are the mandatory capabilities for a Type3 device. + * Only checking capabilities used by current Linux drivers. + */ + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + bitmap_set(expected, CXL_DEV_CAP_MAILBOX_PRIMARY, 1); + bitmap_set(expected, CXL_DEV_CAP_MEMDEV, 1); + + /* + * Checking mandatory caps are there as, at least, a subset of those + * found. + */ + if (!cxl_pci_check_caps(cxlds, expected, found)) { + dev_err(&pdev->dev, + "Expected mandatory capabilities not found: (%08lx - %08lx)\n", + *expected, *found); + return -ENXIO; + } + rc = cxl_pci_type3_init_mailbox(cxlds); if (rc) return rc; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index f656fcd4945f..05f06bfd2c29 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -37,4 +37,7 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, + unsigned long *expected_caps, + unsigned long *current_caps); #endif