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Mon, 16 Dec 2024 10:10:57 -0600 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v8 05/27] cxl: move pci generic code Date: Mon, 16 Dec 2024 16:10:20 +0000 Message-ID: <20241216161042.42108-6-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> References: <20241216161042.42108-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|SA1PR12MB8843:EE_ X-MS-Office365-Filtering-Correlation-Id: ac9310cd-b299-44e3-4cdc-08dd1dec3b7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: fGvRnlX/vUdvF6vt9ILclURXUbwj5NI+IQyEyRgCiEmxCwCeQjioq+ormDRydWxofc+2HTKa6IOZGiOTwaMXJuKDvzug/raNmKDvjfAmbz/jPYhMikh5fH7xQIXg71w3QwB/toKiHXxUMwB5IRLR77s9iPJutxvisfJGJQ9jeOxsFBnRDrJs5WsrvzNoJDJ0uScCwA0bvZXJwSS5TTErPvVUvxLoJuuIzgWuvzCtDmkP2CEeLjv25H82ey6j5cX+ScXKHOkHhuooOixH04J9wmQYPg6tEXrYjIh7u3jEiW2cetgK0uRYSeSuC6XnU1pLhOa52LRW9ugAHznRr8fF1BOU72d22jqUIQk0beONIGj9SFCTg8z2pCmWk42jX+RV+il+ICJjxMhazx3yuaIdErbRwmFZotks1Mae8Q4TXYZBqOp8rQynLQXjXi4bNcYhDhxOwZ86ATadWAzL2aE4jkRp+2ah2WPlwHXhZmSH6B51Itq8jUg+pZUjXPhksE4IK6H3xXwbgzfSKxegiXAxf6fe51AoOXg+QtplF2Jq4JM2DgJ3NKaPJOscl7GMhdz57h3QyzXPBJBBXWjFbNMcBXIYtR2iZc6kD/p+NylnnSjmniWfr+y+Z8uENmcKVfNuJJeTc+v0FtjSXPLFLhQy2Udo6T8BhDtGnYL8ErLrOq1A3ykOvWO0TaVK/2bC8H6M4MmeKdHrX0p0ewIttCS9P0vtHPnpp8wr5707ZOx1PFOAo/mXQUHxbiPF042/Ik1CykmX2l2jU39/Jdr/LpYGUraMwbjm7oMTfp4yHOuO3s8l5dQbb4jXpHEvm/Bb9NiMCCier/ADR+HP/dZ/hjytCtjgty6ZWhepoFs3BSonLxpHxAXc/Nn0WtOGxhumuq7hVWgFnVRT0Xdjk6EXgL3Msr05NDt3uVP3NZaADMgs4SVWIvCVzA5oX4J9XSvz/tTHeOyi2i50VqujlPwWR4QkWjdqOpvWfRoo2B0LJdDTUr+E5cZ/OnXcxfj+FH2sjIZf8F4qHKl8qE8gjolik7sbaqy9BYXJZ9EVVAzvMOM8KzZjY3x/uQmo/9nJbOYOd8D0DEbhMa2Z0IlIOeAPB7YJ3wIktdT6p6E6ppL+SEdwNhY39oJSnPt+sKD+imMXB+WxiQcxRgaavIrLZaBOZ7mC4hd+N9BkeXUkjoIHRfmuHKeT99dQX3K+KG8Dq8wXob85LvfrHJ7OaGJKCHHvCHHr8WPBuyXTPI52bqtIbzGPmjGBWXpYPIm7aRk30beepMe5JMgUWxrknU0mAdPylbb6pGI3aooLaj3o15dhyZH9vp148KaCqSwhQM034/INooTAZS33B9zIck2OBSnI4lUfKFI2EPe2RmMWQ5rrVcq8YxhqsqMZ1t98vJBjG2Lji4eBxrnt5Y7cg/j4UuM6GDIRsR6mzt9NcOoWNQHvZ8brY+OOZBrvl1An1P8GI1X/xQTo7poN97f9uFTOF/CjMPC05UvG/c+uncBa0dujWZB3iSsKE47/I49uA5u3O5e6B6tU X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Dec 2024 16:11:00.2339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac9310cd-b299-44e3-4cdc-08dd1dec3b7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8843 From: Alejandro Lucero Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci.c implements the functionality for a Type3 device initialization. Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be exported and shared with CXL Type2 device initialization. Signed-off-by: Alejandro Lucero Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Fan Ni --- drivers/cxl/core/pci.c | 62 ++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 ++ drivers/cxl/pci.c | 71 ------------------------------------------ 3 files changed, 65 insertions(+), 71 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bc098b2ce55d..3cca3ae438cd 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1034,6 +1034,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); +/* + * Assume that any RCIEP that emits the CXL memory expander class code + * is an RCD + */ +bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, "CXL"); + +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map) +{ + struct cxl_port *port; + struct cxl_dport *dport; + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + port = cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + + put_device(&port->dev); + + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, unsigned long *caps) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) + rc = cxl_rcrb_get_comp_regs(pdev, map); + + if (rc) + return rc; + + return cxl_setup_regs(map, caps); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index eb59019fe5f3..985cca3c3350 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +bool is_cxl_restricted(struct pci_dev *pdev); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, unsigned long *caps); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1fcc53df1217..89056449625f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -467,77 +467,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map, - struct cxl_dport *dport) -{ - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map, - unsigned long *caps) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) { - struct cxl_dport *dport; - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - rc = cxl_rcrb_get_comp_regs(pdev, map, dport); - if (rc) - return rc; - - rc = cxl_dport_map_rcd_linkcap(pdev, dport); - if (rc) - return rc; - - } else if (rc) { - return rc; - } - - return cxl_setup_regs(map, caps); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);