| Message ID | 20250107141015.3367194-14-rrichter@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: Add address translation support and enable AMD Zen5 platforms | expand |
On Tue, Jan 07, 2025 at 03:09:59PM +0100, Robert Richter wrote: > To enable address translation, the endpoint's HPA range must be > translated to each of the parent port's address ranges up to the root > decoder. Traverse the decoder and port hierarchy from the endpoint up > to the root port and apply platform specific translation functions to > determine the next HPA range of the parent port where needed: > > if (cxl_port->to_hpa) > hpa = cxl_port->to_hpa(cxl_decoder, hpa) > > The root port's HPA range is equivalent to the system's SPA range. > > Introduce a callback to translate an HPA range from a port to its > parent. > > Signed-off-by: Robert Richter <rrichter@amd.com> Assuming prior patch holds Reviewed-by: Gregory Price <gourry@gourry.net> > --- > drivers/cxl/cxl.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index be7685fe8a23..49280e0f8840 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -601,6 +601,7 @@ struct cxl_dax_region { > * @parent_dport: dport that points to this port in the parent > * @decoder_ida: allocator for decoder ids > * @reg_map: component and ras register mapping parameters > + * @to_hpa: Callback to translate a child port's decoder address to the port's HPA address range > * @nr_dports: number of entries in @dports > * @hdm_end: track last allocated HDM decoder instance for allocation ordering > * @commit_end: cursor to track highest committed decoder for commit ordering > @@ -621,6 +622,7 @@ struct cxl_port { > struct cxl_dport *parent_dport; > struct ida decoder_ida; > struct cxl_register_map reg_map; > + cxl_to_hpa_fn to_hpa; > int nr_dports; > int hdm_end; > int commit_end; > -- > 2.39.5 >
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index be7685fe8a23..49280e0f8840 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -601,6 +601,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @to_hpa: Callback to translate a child port's decoder address to the port's HPA address range * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @commit_end: cursor to track highest committed decoder for commit ordering @@ -621,6 +622,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + cxl_to_hpa_fn to_hpa; int nr_dports; int hdm_end; int commit_end;
To enable address translation, the endpoint's HPA range must be translated to each of the parent port's address ranges up to the root decoder. Traverse the decoder and port hierarchy from the endpoint up to the root port and apply platform specific translation functions to determine the next HPA range of the parent port where needed: if (cxl_port->to_hpa) hpa = cxl_port->to_hpa(cxl_decoder, hpa) The root port's HPA range is equivalent to the system's SPA range. Introduce a callback to translate an HPA range from a port to its parent. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/cxl.h | 2 ++ 1 file changed, 2 insertions(+)