| Message ID | 20250107141015.3367194-4-rrichter@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: Add address translation support and enable AMD Zen5 platforms | expand |
On Tue, Jan 07, 2025 at 03:09:49PM +0100, Robert Richter wrote: > The comment applies to the check, move it there. > > Signed-off-by: Robert Richter <rrichter@amd.com> > --- > drivers/cxl/core/pci.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index d206378c4cbc..c7050c13f71a 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -419,6 +419,15 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > if (!hdm) > return -ENODEV; > > + /* > + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > + * [High,Low] when HDM operation is enabled the range register values > + * are ignored by the device, but the spec also recommends matching the > + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > + * are expected even though Linux does not require or maintain that > + * match. If at least one DVSEC range is enabled and allowed, skip HDM > + * Decoder Capability Enable. > + */ I agree this comment applies to the earlier check, but wow this function is confusing when compared to what this comment says. For example this line /* * If the HDM Decoder Capability is already enabled then assume * that some other agent like platform firmware set it up. */ if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) return devm_cxl_enable_mem(&port->dev, cxlds); It seems like range register validation logic is unreachable if HDM decoders are enabled? It's unclear. > if (!info->mem_enabled) { > rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); > if (rc) > @@ -454,15 +463,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > return -ENXIO; > } > > - /* > - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > - * [High,Low] when HDM operation is enabled the range register values > - * are ignored by the device, but the spec also recommends matching the > - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > - * are expected even though Linux does not require or maintain that > - * match. If at least one DVSEC range is enabled and allowed, skip HDM > - * Decoder Capability Enable. > - */ > return 0; > } > EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL"); > -- > 2.39.5 >
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index d206378c4cbc..c7050c13f71a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -419,6 +419,15 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, if (!hdm) return -ENODEV; + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges + * are expected even though Linux does not require or maintain that + * match. If at least one DVSEC range is enabled and allowed, skip HDM + * Decoder Capability Enable. + */ if (!info->mem_enabled) { rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); if (rc) @@ -454,15 +463,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, return -ENXIO; } - /* - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base - * [High,Low] when HDM operation is enabled the range register values - * are ignored by the device, but the spec also recommends matching the - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges - * are expected even though Linux does not require or maintain that - * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. - */ return 0; } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL");
The comment applies to the check, move it there. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/core/pci.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)