| Message ID | 20250207153753.418849-4-rrichter@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl: Address translation support, part 1: Cleanups and refactoring | expand |
On Fri, Feb 07, 2025 at 04:37:38PM +0100, Robert Richter wrote: > The comment applies to the check, move it there. > > Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net>
Do we have any limitation for HDM Decoder Range in Linux Kernel ? We has observed that Linux might be hung if range is larger than 8TB. Jim
On Fri, Feb 07, 2025 at 09:36:08PM +0000, Jim Kao wrote: > Do we have any limitation for HDM Decoder Range in Linux Kernel ? > We has observed that Linux might be hung if range is larger than 8TB. > > Jim > Do you have any additional details? dmesg/core dumps, etc? Seems pretty suspicious that it happens right on the 44-bit boundary.
On 07.02.25 17:19:50, Gregory Price wrote: > On Fri, Feb 07, 2025 at 09:36:08PM +0000, Jim Kao wrote: > > Do we have any limitation for HDM Decoder Range in Linux Kernel ? > > We has observed that Linux might be hung if range is larger than 8TB. > > > > Jim > > > > Do you have any additional details? dmesg/core dumps, etc? > > Seems pretty suspicious that it happens right on the 44-bit boundary. I am not aware of limitations from CXL spec or driver. AMD platforms support a much larger physical address range. -Robert
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index f8e22bc278c3..c49efc419285 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -419,6 +419,15 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, if (!hdm) return -ENODEV; + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges + * are expected even though Linux does not require or maintain that + * match. If at least one DVSEC range is enabled and allowed, skip HDM + * Decoder Capability Enable. + */ if (!info->mem_enabled) { rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); if (rc) @@ -454,15 +463,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, return -ENXIO; } - /* - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base - * [High,Low] when HDM operation is enabled the range register values - * are ignored by the device, but the spec also recommends matching the - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges - * are expected even though Linux does not require or maintain that - * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. - */ return 0; } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL");
The comment applies to the check, move it there. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/core/pci.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)