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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2025 01:50:06.5849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d30beb38-5b21-401b-9e2a-08dd6cd1b327 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022573.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8695 The cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() functions are unnecessary helper function and only used for Endpoints. Remove these functions because they are not necessary and do not align with a common handling API for all CXL devices' errors. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index f2139b382839..a67925dfdbe1 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -670,11 +670,6 @@ static void __cxl_handle_cor_ras(struct device *cxl_dev, struct device *pcie_dev trace_cxl_aer_correctable_error(cxl_dev, pcie_dev, serial, status); } -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, NULL, cxlds->serial, cxlds->regs.ras); -} - /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { @@ -732,14 +727,8 @@ static pci_ers_result_t __cxl_handle_ras(struct device *cxl_dev, struct device * return PCI_ERS_RESULT_PANIC; } -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(&cxlds->cxlmd->dev, NULL, cxlds->serial, cxlds->regs.ras); -} - #ifdef CONFIG_PCIEAER_CXL - void cxl_port_cor_error_detected(struct device *cxl_dev, struct cxl_prot_error_info *err_info) { @@ -868,7 +857,8 @@ void cxl_cor_error_detected(struct device *dev, struct cxl_prot_error_info *err_ if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); - cxl_handle_endpoint_cor_ras(cxlds); + __cxl_handle_cor_ras(&cxlds->cxlmd->dev, &pdev->dev, + cxlds->serial, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -907,7 +897,8 @@ pci_ers_result_t cxl_error_detected(struct device *dev, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue = cxl_handle_endpoint_ras(cxlds); + ue = __cxl_handle_ras(&cxlds->cxlmd->dev, &pdev->dev, + cxlds->serial, cxlds->regs.ras); } if (ue)