| Message ID | 20250407192734.70631-1-Smita.KoralahalliChannabasappa@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl/core/regs.c: Skip Memory Space Enable check for RCD and RCH Ports | expand |
On 07.04.25 19:27:34, Smita Koralahalli wrote: > According to CXL r3.2 section 8.2.1.2, the PCI_COMMAND register fields, > including Memory Space Enable bit, have no effect on the behavior of an > RCD Upstream Port. Retaining this check may incorrectly cause > cxl_pci_probe() to fail on a valid RCD upstream Port. > > While the specification is explicit only for RCD Upstream Ports, this > check is solely for accessing the RCRB, which is always mapped through > memory space. Therefore, its safe to remove the check entirely. In > practice, firmware reliably enables the Memory Space Enable bit for > RCH Downstream Ports and no failures have been observed. > > Removing the check simplifies the code and avoids unnecessary > special-casing, while relying on BIOS/firmware to configure devices > correctly. Moreover, any failures due to inaccessible RCRB regions > will still be caught either in __rcrb_to_component() or while > parsing the component register block. > > The following failure was observed in dmesg when the check was present: > cxl_pci 0000:7f:00.0: No component registers (-6) > > Fixes: d5b1a27143cb ("cxl/acpi: Extract component registers of restricted hosts from RCRB") > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Robert Richter <rrichter@amd.com> Thanks Smita. > --- > drivers/cxl/core/regs.c | 4 ---- > 1 file changed, 4 deletions(-)
On 4/7/25 12:27 PM, Smita Koralahalli wrote: > According to CXL r3.2 section 8.2.1.2, the PCI_COMMAND register fields, > including Memory Space Enable bit, have no effect on the behavior of an > RCD Upstream Port. Retaining this check may incorrectly cause > cxl_pci_probe() to fail on a valid RCD upstream Port. > > While the specification is explicit only for RCD Upstream Ports, this > check is solely for accessing the RCRB, which is always mapped through > memory space. Therefore, its safe to remove the check entirely. In > practice, firmware reliably enables the Memory Space Enable bit for > RCH Downstream Ports and no failures have been observed. > > Removing the check simplifies the code and avoids unnecessary > special-casing, while relying on BIOS/firmware to configure devices > correctly. Moreover, any failures due to inaccessible RCRB regions > will still be caught either in __rcrb_to_component() or while > parsing the component register block. > > The following failure was observed in dmesg when the check was present: > cxl_pci 0000:7f:00.0: No component registers (-6) > > Fixes: d5b1a27143cb ("cxl/acpi: Extract component registers of restricted hosts from RCRB") > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/core/regs.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c > index 117c2e94c761..5ca7b0eed568 100644 > --- a/drivers/cxl/core/regs.c > +++ b/drivers/cxl/core/regs.c > @@ -581,7 +581,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri > resource_size_t rcrb = ri->base; > void __iomem *addr; > u32 bar0, bar1; > - u16 cmd; > u32 id; > > if (which == CXL_RCRB_UPSTREAM) > @@ -603,7 +602,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri > } > > id = readl(addr + PCI_VENDOR_ID); > - cmd = readw(addr + PCI_COMMAND); > bar0 = readl(addr + PCI_BASE_ADDRESS_0); > bar1 = readl(addr + PCI_BASE_ADDRESS_1); > iounmap(addr); > @@ -618,8 +616,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri > dev_err(dev, "Failed to access Downstream Port RCRB\n"); > return CXL_RESOURCE_NONE; > } > - if (!(cmd & PCI_COMMAND_MEMORY)) > - return CXL_RESOURCE_NONE; > /* The RCRB is a Memory Window, and the MEM_TYPE_1M bit is obsolete */ > if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO)) > return CXL_RESOURCE_NONE;
On 4/7/2025 2:27 PM, Smita Koralahalli wrote: > According to CXL r3.2 section 8.2.1.2, the PCI_COMMAND register fields, > including Memory Space Enable bit, have no effect on the behavior of an > RCD Upstream Port. Retaining this check may incorrectly cause > cxl_pci_probe() to fail on a valid RCD upstream Port. > > While the specification is explicit only for RCD Upstream Ports, this > check is solely for accessing the RCRB, which is always mapped through > memory space. Therefore, its safe to remove the check entirely. In > practice, firmware reliably enables the Memory Space Enable bit for > RCH Downstream Ports and no failures have been observed. > > Removing the check simplifies the code and avoids unnecessary > special-casing, while relying on BIOS/firmware to configure devices > correctly. Moreover, any failures due to inaccessible RCRB regions > will still be caught either in __rcrb_to_component() or while > parsing the component register block. > > The following failure was observed in dmesg when the check was present: > cxl_pci 0000:7f:00.0: No component registers (-6) > > Fixes: d5b1a27143cb ("cxl/acpi: Extract component registers of restricted hosts from RCRB") > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> > --- Reviewed-by: Terry Bowman <terry.bowman@amd.com>
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 117c2e94c761..5ca7b0eed568 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -581,7 +581,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri resource_size_t rcrb = ri->base; void __iomem *addr; u32 bar0, bar1; - u16 cmd; u32 id; if (which == CXL_RCRB_UPSTREAM) @@ -603,7 +602,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri } id = readl(addr + PCI_VENDOR_ID); - cmd = readw(addr + PCI_COMMAND); bar0 = readl(addr + PCI_BASE_ADDRESS_0); bar1 = readl(addr + PCI_BASE_ADDRESS_1); iounmap(addr); @@ -618,8 +616,6 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri dev_err(dev, "Failed to access Downstream Port RCRB\n"); return CXL_RESOURCE_NONE; } - if (!(cmd & PCI_COMMAND_MEMORY)) - return CXL_RESOURCE_NONE; /* The RCRB is a Memory Window, and the MEM_TYPE_1M bit is obsolete */ if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO)) return CXL_RESOURCE_NONE;
According to CXL r3.2 section 8.2.1.2, the PCI_COMMAND register fields, including Memory Space Enable bit, have no effect on the behavior of an RCD Upstream Port. Retaining this check may incorrectly cause cxl_pci_probe() to fail on a valid RCD upstream Port. While the specification is explicit only for RCD Upstream Ports, this check is solely for accessing the RCRB, which is always mapped through memory space. Therefore, its safe to remove the check entirely. In practice, firmware reliably enables the Memory Space Enable bit for RCH Downstream Ports and no failures have been observed. Removing the check simplifies the code and avoids unnecessary special-casing, while relying on BIOS/firmware to configure devices correctly. Moreover, any failures due to inaccessible RCRB regions will still be caught either in __rcrb_to_component() or while parsing the component register block. The following failure was observed in dmesg when the check was present: cxl_pci 0000:7f:00.0: No component registers (-6) Fixes: d5b1a27143cb ("cxl/acpi: Extract component registers of restricted hosts from RCRB") Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- drivers/cxl/core/regs.c | 4 ---- 1 file changed, 4 deletions(-)