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[217.229.16.64]) by smtp.gmail.com with ESMTPSA id 143sm129890035wml.14.2019.01.24.10.02.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 Jan 2019 10:02:55 -0800 (PST) From: Thierry Reding To: Thierry Reding Subject: [PATCH v2 00/13] drm/tegra: Fix IOVA space on Tegra186 and later Date: Thu, 24 Jan 2019 19:02:41 +0100 Message-Id: <20190124180254.20080-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko , dri-devel@lists.freedesktop.org, Mikko Perttunen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Tegra186 and later are different from earlier generations in that they use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves slightly differently in that the geometry for IOMMU domains is set only after a device was attached to it. This is to make sure that the SMMU instance that the domain belongs to is known, because each instance can have a different input address space (i.e. geometry). Work around this by moving all IOVA allocations to a point where the geometry of the domain is properly initialized. This second version of the series addresses all review comments and adds a number of patches that will actually allow host1x to work with an SMMU enabled on Tegra186. The patches also add programming required to address the full 40 bits of address space. This supersedes the following patch: https://patchwork.kernel.org/patch/10775579/ Thierry Thierry Reding (13): gpu: host1x: Set up stream ID table gpu: host1x: Program the channel stream ID gpu: host1x: Support 40-bit addressing gpu: host1x: Use direct DMA with IOMMU API usage gpu: host1x: Restrict IOVA space to DMA mask gpu: host1x: Supports 40-bit addressing on Tegra186 drm/tegra: Store parent pointer in Tegra DRM clients drm/tegra: vic: Load firmware on demand drm/tegra: Setup shared IOMMU domain after initialization drm/tegra: Restrict IOVA space to DMA mask drm/tegra: vic: Do not clear driver data drm/tegra: vic: Support stream ID register programming arm64: tegra: Enable SMMU for VIC on Tegra186 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + drivers/gpu/drm/tegra/drm.c | 57 +++++++++------- drivers/gpu/drm/tegra/drm.h | 1 + drivers/gpu/drm/tegra/vic.c | 75 ++++++++++++++++----- drivers/gpu/drm/tegra/vic.h | 9 +++ drivers/gpu/host1x/cdma.c | 11 ++- drivers/gpu/host1x/dev.c | 49 ++++++++++++-- drivers/gpu/host1x/dev.h | 8 +++ drivers/gpu/host1x/hw/cdma_hw.c | 13 +++- drivers/gpu/host1x/hw/channel_hw.c | 40 +++++++++-- drivers/gpu/host1x/hw/host1x06_hardware.h | 6 ++ drivers/gpu/host1x/hw/host1x07_hardware.h | 6 ++ drivers/gpu/host1x/hw/hw_host1x06_channel.h | 11 +++ drivers/gpu/host1x/hw/hw_host1x07_channel.h | 11 +++ 14 files changed, 241 insertions(+), 57 deletions(-) create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_channel.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_channel.h