From patchwork Tue Apr 2 09:36:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wangyan wang X-Patchwork-Id: 10882909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64CBD1390 for ; Wed, 3 Apr 2019 06:57:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D21B2866D for ; Wed, 3 Apr 2019 06:57:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41BBD2896F; Wed, 3 Apr 2019 06:57:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 006F42866D for ; Wed, 3 Apr 2019 06:57:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EEE666E8DA; Wed, 3 Apr 2019 06:57:23 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by gabe.freedesktop.org (Postfix) with ESMTP id 0044C6E337 for ; Tue, 2 Apr 2019 09:36:15 +0000 (UTC) X-UUID: 17d815fc41da487ea0cf91aeb07a4736-20190402 X-UUID: 17d815fc41da487ea0cf91aeb07a4736-20190402 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 951479963; Tue, 02 Apr 2019 17:36:10 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 2 Apr 2019 17:36:08 +0800 Received: from mszsdclx1067.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 2 Apr 2019 17:36:07 +0800 From: wangyan wang To: Michael Turquette , Stephen Boyd , CK Hu Subject: [PATCH V8 0/5] make mt7623 clock of hdmi stable Date: Tue, 2 Apr 2019 17:36:00 +0800 Message-ID: <20190402093605.82004-1-wangyan.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Wed, 03 Apr 2019 06:57:22 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryder Lee , srv_heupstream@mediatek.com, chunhui dai , David Airlie , Sean Wang , linux-kernel@vger.kernel.org, wangyan wang , linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Matthias Brugger , Colin Ian King , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Wangyan Wang V8 adopt maintainer's suggestion. Here is the change list between V7 & V8 1. Make title more clear in patch commit message. 2. To make MT2701 HDMI stable, TVDPLL should not be adjusted and it's the parent clock of HDMI phy, so HDMI phy could not adjust parent rate. there are 3 steps to make MT2701 HDMI stable. 1). remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent in "drm/mediatek: remove flag ...". 2). Using new factor for tvdpll in mt2701 to match divider of DPI in mt2701 in "drm/mediatek: using new...". 3). No change parent rate in round_rate() for mt2701 hdmi phy in "drm/mediatek: no change parent...". 3. Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Wangyan Wang (5): drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy drm/mediatek: fix the rate and divder of hdmi phy for MT2701 drm/mediatek: using new factor for tvdpll in MT2701 drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy drm/mediatek: make implementation of recalc_rate() to match the definition drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 35 +++--------------- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 5 +-- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 50 ++++++++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 ++++++++++++ 5 files changed, 76 insertions(+), 45 deletions(-)