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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id 63sm32395096wri.25.2019.10.15.04.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 04:33:18 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 0/3] drm/meson: implement RDMA for AFBC reset on vsync Date: Tue, 15 Oct 2019 13:33:14 +0200 Message-Id: <20191015113317.8870-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=uCg5k9ZAbrV4GjqeNyvcbYZv8xwqr0DzEBoAapcuUF4=; b=G3fnqlIagUgIzXqdwH5ad+9LBWcqrcYgJb30mqH/lJuHES/QADTo7Q79HHx38JFeTw iBIq6Rqp2ebm7x8t/kgaoAOp5et70+eGTzJos/0qlpHJndcaijozRSQnJL5Pb5SnNQQU 76EUgt79m8OWixvlxO89x8wmWLHnZEU5HTqvG3Kx1S6J5F6MtbDiVsqaEh2P25bnBjQo 1qCm1lmgxaAGgzHHdCzFXDtXxj8y9Fb4mYBGRibzBCvjCSpudY/a0KPWikrkqfo7SO1S Nfl6Yz5EX2IvwfF6VL7q8qnMU7bhNWi1lRgDZt45RxD56XeB/EerY8fY66o2NLxJt+pB NTzw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq. The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches. For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW. When enabled, the RDMA is enabled to rewritte the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane. The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync. Neil Armstrong (3): drm/meson: add RDMA register bits defines drm/meson: add RDMA module driver drm/meson: use RDMA to reconfigure AFBC on vsync drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_crtc.c | 27 ++---- drivers/gpu/drm/meson/meson_drv.c | 14 ++- drivers/gpu/drm/meson/meson_drv.h | 6 ++ drivers/gpu/drm/meson/meson_osd_afbcd.c | 100 ++++++++++--------- drivers/gpu/drm/meson/meson_rdma.c | 123 ++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_rdma.h | 20 ++++ drivers/gpu/drm/meson/meson_registers.h | 48 +++++++++ 8 files changed, 273 insertions(+), 67 deletions(-) create mode 100644 drivers/gpu/drm/meson/meson_rdma.c create mode 100644 drivers/gpu/drm/meson/meson_rdma.h