From patchwork Tue Dec 3 14:35:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lipski, Mikita" X-Patchwork-Id: 11271411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53CB2138C for ; Tue, 3 Dec 2019 14:35:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C16720659 for ; Tue, 3 Dec 2019 14:35:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C16720659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11DD56E78F; Tue, 3 Dec 2019 14:35:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770040.outbound.protection.outlook.com [40.107.77.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A37D6E78A; Tue, 3 Dec 2019 14:35:43 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OZ5XNiBE6QSuMxbtOqkjXsYooBf4pKprruvxAJikZiWSb8lkuFlevwWDENUaI1keVEq1J3gAJrsumGht4VhJ4vADmmbr6feT6oO71HtTwGXlLQ3mMJaCMe9lKRhOQUajFbMmnH3pEiTIWs9PqBsJsMQAHcQ3PbySnYOaweZeJ7FoMtMb+6DpWq6hbcdwVq/VUFaRUTr/ALF0ldC7RtUTTeyUevfwXYXr8ppiLqYKYAaB5lvgafr0ZEpo92k2HBP81HX2VnirKp5WNEZNWrCsOwSKmIAaviI0B7YIXBKQukKfhO36zCOpy9/qGQA9JA2wbEmQDocVXGZyHnVgC/zT6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bTy3P8e4ZAHcq4A0FPlYV0BNr6tbXL5F8onOkkQ0QBI=; b=mHDfdyTYJqkavUqmCEpJY8qqIwIUh4YMXNGwvTcVIHHe8KgVdNhHUMSRWY5ggrvT328JemZjEd8Ex3FtJJ0th7ZTwEc7w+K1Hi9b0BuUcvvjxFqYC+nThGs4+Iu8zyZQ3vWEZA9Eif6COQv3FvjJt60BmT+klRA1f5WWD+/4+5uFeH6S7wfW462guPtaC6j/nNwR1R0sAw7KRqTudqMkY0MYrV4lcOjbbsQBtyKk2z4g3NMJttA9ZzpIz3WcmEQQRi2KCAYeZvLdlJ2i2NSjze8JZcXeeGYW5h4ffPND0mRxoFcJ8UMgGqPxVDsmJMrwaOOBzW0Yr9nvfrNFNMKzjA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=permerror action=none header.from=amd.com; dkim=none (message not signed); arc=none Received: from DM6PR12CA0022.namprd12.prod.outlook.com (2603:10b6:5:1c0::35) by BY5PR12MB4194.namprd12.prod.outlook.com (2603:10b6:a03:210::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.17; Tue, 3 Dec 2019 14:35:41 +0000 Received: from DM6NAM11FT054.eop-nam11.prod.protection.outlook.com (2a01:111:f400:7eaa::201) by DM6PR12CA0022.outlook.office365.com (2603:10b6:5:1c0::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2495.18 via Frontend Transport; Tue, 3 Dec 2019 14:35:41 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXMB02.amd.com (165.204.84.17) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2451.23 via Frontend Transport; Tue, 3 Dec 2019 14:35:41 +0000 Received: from SATLEXMB01.amd.com (10.181.40.142) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 3 Dec 2019 08:35:40 -0600 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 3 Dec 2019 08:35:40 -0600 From: To: Subject: [PATCH v8 00/17] DSC MST support for DRM and AMDGPU Date: Tue, 3 Dec 2019 09:35:13 -0500 Message-ID: <20191203143530.27262-1-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(39860400002)(346002)(136003)(376002)(428003)(189003)(199004)(2351001)(6916009)(26005)(7696005)(51416003)(50466002)(426003)(81156014)(356004)(8676002)(48376002)(2616005)(336012)(6666004)(1076003)(4326008)(81166006)(50226002)(450100002)(186003)(478600001)(8936002)(70206006)(5660300002)(54906003)(14444005)(86362001)(305945005)(70586007)(36756003)(2906002)(53416004)(316002)(2876002)(16586007)(16060500001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY5PR12MB4194; H:SATLEXMB02.amd.com; FPR:; SPF:None; LANG:en; PTR:InfoDomainNonexistent; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 971e155d-6d46-4aae-4326-08d777fe12ba X-MS-TrafficTypeDiagnostic: BY5PR12MB4194: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-Forefront-PRVS: 02408926C4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AkYI4zWRitPFR1iEk3r3lP7fl000RmJnbjLvPbdiOmDVwLkUtN9sUEC3G0/fhLijSWC4vCqdf4MEZzitU9DoyoV/+v/FSKiGBy90Ydlur3sM05RPZFOuYWILl9cLms0+1TIxtOrHPRhUi1BHSvj+80lY7EPDyMmYIcgJYWKKOs0hu6Qu7A+v+23NiqzVwjKjA929tdRJDupuqAaFp5GOs/vko0+CgyDgcTUYfHrIz8sPooH26TPc6dtS7fETMYvc0OWJXjk3nXTywp2iAb8kFAkjhXPlxxDSuznknrGXiCdLyb3oAETYk3oj4Au1V2z+mD6GxeJXu6X4jmByQypZ0ikTMbGg8Cn8Bw7IRjT/sYQ1oT1pRKVhG1d9wFE6smF2XB52+TCagP2yiEXFQKH/Rpmq6/ZrAaFm9+yAV6IQ93/wr3lzSUy2h/+u6USIPmvJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2019 14:35:41.4976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 971e155d-6d46-4aae-4326-08d777fe12ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4194 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bTy3P8e4ZAHcq4A0FPlYV0BNr6tbXL5F8onOkkQ0QBI=; b=a7sgCLz7GM9oR9y7H5/GDxGUP7mK3XJ4YQujem1f1tRZdcYaIPDvoatf+3FBxRhjJTMt82JgQQgk0ZYDVUfsi/G434h5/9kOIUUrIg4EYL60tVn+ZyjuhyT47PXmVCdMjL1QPYKQjFNT3DMg8PTMlcy5aXy04/19mqKuaT1TMvs= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mikita Lipski , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mikita Lipski This set of patches is a continuation of DSC enablement patches for AMDGPU. This set enables DSC on MST. It also contains implementation of both encoder and connector atomic check routines. These patches have been introduced in multiple iterations to the mailing list before. These patches were developed by David Francis as part of his work on DSC. v2: squashed previously 3 separate atomic check patches, separate atomic check for dsc connectors, track vcpi and pbn on connectors. v3: Moved modeset trigger on affected MST displays to DRM v4: Fix warnings, use current mode's bpc rather than display's maximum capable one v5: Moving branch's bandwidth validation to DRM, Added function to enable DSC per port in DRM v6: Compute fair share uses DRM helper for BW validation v7: Add helper to overwrite PBN divider per slot, Add helper function to trigger modeset on affected DSC connectors in DRM v8: Rebased on top of the MST refactor patches that were on DRM-tip Some cosmetic and cleanup changes David Francis (9): drm/dp_mst: Add PBN calculation for DSC modes drm/dp_mst: Parse FEC capability on MST ports drm/dp_mst: Add MST support to DP DPCD R/W functions drm/dp_mst: Fill branch->num_ports drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux drm/amd/display: Initialize DSC PPS variables to 0 drm/amd/display: Validate DSC caps on MST endpoints drm/amd/display: Write DSC enable to MST DPCD drm/amd/display: MST DSC compute fair share Mikita Lipski (8): drm/dp_mst: Add new quirk for Synaptics MST hubs drm/dp_mst: Manually overwrite PBN divider for calculating timeslots drm/dp_mst: Add DSC enablement helpers to DRM drm/dp_mst: Add branch bandwidth validation to MST atomic check drm/amd/display: Add PBN per slot calculation for DSC drm/amd/display: Recalculate VCPI slots for new DSC connectors drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs drm/amd/display: Trigger modesets on MST DSC connectors .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 117 ++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 399 +++++++++++++++++- .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 5 + .../drm/amd/display/dc/core/dc_link_hwss.c | 3 + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 + drivers/gpu/drm/drm_dp_aux_dev.c | 12 +- drivers/gpu/drm/drm_dp_helper.c | 32 +- drivers/gpu/drm/drm_dp_mst_topology.c | 395 ++++++++++++++++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_helper.h | 7 + include/drm/drm_dp_mst_helper.h | 19 +- 17 files changed, 988 insertions(+), 44 deletions(-)