From patchwork Mon Sep 14 05:56:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11772915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C83B14F6 for ; Mon, 14 Sep 2020 06:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36A0D207C3 for ; Mon, 14 Sep 2020 06:23:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36A0D207C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F2306E152; Mon, 14 Sep 2020 06:22:57 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41EEA6E152; Mon, 14 Sep 2020 06:22:56 +0000 (UTC) IronPort-SDR: zcNGAMiunBj2R36IPl3d0bIpLov1gqN9iyV3Yvp4kHHkbPIWxbaqoZDrBiMU798oJvVqh6Lube 5pP8R5RBG2kA== X-IronPort-AV: E=McAfee;i="6000,8403,9743"; a="159965653" X-IronPort-AV: E=Sophos;i="5.76,425,1592895600"; d="scan'208";a="159965653" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2020 23:22:55 -0700 IronPort-SDR: T/cA4MObcu8UtKSTzZ9myNyHJ79JjhnK92VI67DNqh2Yef0jqODt/nrHv4qyMV9OXN/9L6ddfg YRGme3Nzrvgw== X-IronPort-AV: E=Sophos;i="5.76,425,1592895600"; d="scan'208";a="287536596" Received: from karthik-2012-client-platform.iind.intel.com ([10.223.74.217]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 13 Sep 2020 23:22:51 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v8 0/8] Asynchronous flip implementation for i915 Date: Mon, 14 Sep 2020 11:26:25 +0530 Message-Id: <20200914055633.21109-1-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Without async flip support in the kernel, fullscreen apps where game resolution is equal to the screen resolution, must perform an extra blit per frame prior to flipping. Asynchronous page flips will also boost the FPS of Mesa benchmarks. v2: -Few patches have been squashed and patches have been shuffled as per the reviews on the previous version. v3: -Few patches have been squashed and patches have been shuffled as per the reviews on the previous version. v4: -Made changes to fix the sequence and time stamp issue as per the comments received on the previous version. -Timestamps are calculated using the flip done time stamp and current timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used for timestamp calculations. -Event is sent from the interrupt handler immediately using this updated timestamps and sequence. -Added more state checks as async flip should only allow change in plane surface address and nothing else should be allowed to change. -Added a separate plane hook for async flip. -Need to find a way to reject fbc enabling if it comes as part of this flip as bspec states that changes to FBC are not allowed. v5: -Fixed the Checkpatch and sparse warnings. v6: -Reverted back to the old timestamping code as per the feedback received. -Added documentation. v7: -Changes in intel_atomic_check_async() -Add vfunc for skl_program_async_surface_address() v8: -Add WA for older platforms with double buffered async address update enable bit. Test-with: <20200908061001.20302-1-karthik.b.s@intel.com> Karthik B S (8): drm/i915: Add enable/disable flip done and flip done handler drm/i915: Add support for async flips in I915 drm/i915: Add checks specific to async flips drm/i915: Do not call drm_crtc_arm_vblank_event in async flips drm/i915: Add dedicated plane hook for async flip case drm/i915: WA for platforms with double buffered adress update enable bit Documentation/gpu: Add asynchronous flip documentation for i915 drm/i915: Enable async flips in i915 Documentation/gpu/i915.rst | 6 + .../gpu/drm/i915/display/intel_atomic_plane.c | 7 + drivers/gpu/drm/i915/display/intel_display.c | 201 ++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/display/intel_sprite.c | 30 +++ drivers/gpu/drm/i915/i915_irq.c | 52 +++++ drivers/gpu/drm/i915/i915_irq.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 1 + 8 files changed, 302 insertions(+)