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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id q25sm390552pfs.152.2021.04.28.12.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Apr 2021 12:33:25 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Subject: [PATCH 0/2] drm/msm: Smooth out ringbuffer-full handling Date: Wed, 28 Apr 2021 12:36:47 -0700 Message-Id: <20210428193654.1498482-1-robdclark@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , Marijn Suijten , Jonathan Marek , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Sharat Masetty , Konrad Dybcio , Akhil P Oommen , Douglas Anderson , "Kristian H. Kristensen" , AngeloGioacchino Del Regno , Dave Airlie , Jordan Crouse , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark With some recent userspace work to allow more rendering to be merged into a single SUBMIT ioctl, I realized we have some sharp edges around running out of free ringbuffer space. 1) Currently we only flush once all the cmds (or rather IBs to the cmd buffer) are written into the ringbuffer. Which places a restriction that the submit must fit in the rb. Which means slightly less than 2k cmds per submit, after accounting for some of the other packets needed. 2) Currently, for devices that use RPTR shadow, we only write the CP_WHERE_AM_I packet at the end of the submit, so we aren't seeing partial progress that the GPU is making chewing through previous large submits 3) We spin for up to 1sec waiting for rb space, and then give up and proceed to overwrite the packets that that CP is currently chewing on.. which goes badly. If userspace is submitting >1sec of work per submit ioctl, this means we spin for a long time, and then corrupt the rb anyways. This patchset doesn't completely address #1. And in general we don't want to be uninteruptably blocking for so much time.. but this will require some more extensive changes. What it does do is address #2 by periodically emitting a CP_WHERE_AM_I, and #3 by adding detection and error handling for rb overflow, returning -ENOSPC when that happens. Rob Clark (2): drm/msm: Handle ringbuffer overflow drm/msm: Periodically update RPTR shadow drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 32 ++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 +++++++++++++++++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 24 +++++++++++++++++- drivers/gpu/drm/msm/msm_gem_submit.c | 7 +++++- drivers/gpu/drm/msm/msm_gpu.c | 33 +++++++++++++++++++++++-- drivers/gpu/drm/msm/msm_gpu.h | 2 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 5 ++++ 7 files changed, 117 insertions(+), 16 deletions(-)