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[00/53] Begin enabling Xe_HP SDV and DG2 platforms

Message ID 20210701202427.1547543-1-matthew.d.roper@intel.com (mailing list archive)
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Series Begin enabling Xe_HP SDV and DG2 platforms | expand

Message

Matt Roper July 1, 2021, 8:23 p.m. UTC 
This series provides some of the initial enablement patches for two
upcoming discrete GPUs:
 * XeHP SDV:  Xe_HP (version 12.50) graphics IP, no display IP
 * DG2:  Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP

Both platforms will need additional enablement patches beyond what's
present in this series before they're truly usable, including various
LMEM and GuC work that's already happening separately.  The new
features/functionality that these platforms bring (such as multi-tile
support, dedicated compute engines, etc.) may be referenced in passing
in some of these patches but will be fully enabled in future series.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>


Akeem G Abodunrin (1):
  drm/i915/dg2: Add new LRI reg offsets

Animesh Manna (1):
  drm/i915/dg2: Update to bigjoiner path

Ankit Nautiyal (1):
  drm/i915/dg2: Configure PCON in DP pre-enable path

Anusha Srivatsa (2):
  drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP
    enable
  drm/i915/display/dsc: Set BPP in the kernel

Daniele Ceraolo Spurio (1):
  drm/i915/xehp: handle new steering options

Gwan-gyeong Mun (1):
  drm/i915/dg2: Update lane disable power state during PSR

John Harrison (4):
  drm/i915/selftests: Allow for larger engine counts
  drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
  drm/i915/xehp: Extra media engines - Part 2 (interrupts)
  drm/i915/xehp: Extra media engines - Part 3 (reset)

José Roberto de Souza (1):
  drm/i915/dg2: Add DG2 to the PSR2 defeature list

Lucas De Marchi (5):
  drm/i915: Add "release id" version
  drm/i915: Add XE_HP initial definitions
  drm/i915/xehpsdv: add initial XeHP SDV definitions
  drm/i915/xehpsdv: Define MOCS table for XeHP SDV
  drm/i915/xehpsdv: factor out function to read RP_STATE_CAP

Matt Roper (29):
  drm/i915/xehp: Xe_HP forcewake support
  drm/i915/xehp: Define multicast register ranges
  drm/i915/xehp: Loop over all gslices for INSTDONE processing
  drm/i915/xehpsdv: Add maximum sseu limits
  drm/i915/xehpsdv: Define steering tables
  drm/i915/xehpsdv: Read correct RP_STATE_CAP register
  drm/i915/dg2: add DG2 platform info
  drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
  drm/i915/dg2: Add forcewake table
  drm/i915/dg2: Update LNCF steering ranges
  drm/i915/dg2: Add SQIDI steering
  drm/i915/dg2: Maintain backward-compatible nested batch behavior
  drm/i915/dg2: Report INSTDONE_GEOM values in error state
  drm/i915/dg2: Define MOCS table for DG2
  drm/i915/dg2: Add fake PCH
  drm/i915/dg2: Add cdclk table and reference clock
  drm/i915/dg2: Skip shared DPLL handling
  drm/i915/dg2: Don't wait for AUX power well enable ACKs
  drm/i915/dg2: Setup display outputs
  drm/i915/dg2: Add dbuf programming
  drm/i915/dg2: Don't program BW_BUDDY registers
  drm/i915/dg2: Don't read DRAM info
  drm/i915/dg2: DG2 has fixed memory bandwidth
  drm/i915/dg2: Add MPLLB programming for SNPS PHY
  drm/i915/dg2: Add MPLLB programming for HDMI
  drm/i915/dg2: Add vswing programming for SNPS phys
  drm/i915/dg2: Update modeset sequences
  drm/i915/dg2: Classify DG2 PHY types
  drm/i915/dg2: Wait for SNPS PHY calibration during display init

Matthew Auld (1):
  drm/i915/xehp: Changes to ss/eu definitions

Paulo Zanoni (1):
  drm/i915: Fork DG1 interrupt handler

Prathap Kumar Valsan (1):
  drm/i915/xehp: New engine context offsets

Stuart Summers (2):
  drm/i915/xehp: Handle new device context ID format
  drm/i915/xehpsdv: Add compute DSS type

Tvrtko Ursulin (1):
  drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based

Venkata Sandeep Dhanalakota (1):
  drm/i915/gen12: Use fuse info to enable SFC

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_bw.c       |  24 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  24 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 165 +++-
 drivers/gpu/drm/i915/display/intel_display.c  |  94 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   1 +
 .../drm/i915/display/intel_display_debugfs.c  | 103 ++-
 .../drm/i915/display/intel_display_power.c    |  25 +
 .../drm/i915/display/intel_display_power.h    |  10 +
 .../drm/i915/display/intel_display_types.h    |  18 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  23 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   5 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  11 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 862 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_snps_phy.h |  35 +
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c       |   8 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |   7 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     | 144 ++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |  29 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  78 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            |  66 +-
 drivers/gpu/drm/i915/gt/intel_gt.h            |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c        |  13 +-
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   7 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 156 +++-
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |   2 +
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  66 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c   |   1 +
 drivers/gpu/drm/i915/gt/intel_reset.c         |   6 +
 drivers/gpu/drm/i915/gt/intel_rps.c           |  19 +-
 drivers/gpu/drm/i915/gt/intel_rps.h           |   1 +
 drivers/gpu/drm/i915/gt/intel_sseu.c          | 116 ++-
 drivers/gpu/drm/i915/gt/intel_sseu.h          |  20 +-
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c  |   2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 175 +++-
 drivers/gpu/drm/i915/gt/selftest_execlists.c  |  10 +-
 .../gpu/drm/i915/gt/selftest_workarounds.c    |  32 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   8 +-
 drivers/gpu/drm/i915/i915_drv.h               |  48 +-
 drivers/gpu/drm/i915/i915_getparam.c          |   6 +-
 drivers/gpu/drm/i915/i915_gpu_error.c         |  36 +-
 drivers/gpu/drm/i915/i915_irq.c               | 141 ++-
 drivers/gpu/drm/i915/i915_pci.c               |  63 +-
 drivers/gpu/drm/i915/i915_perf.c              |  29 +-
 drivers/gpu/drm/i915/i915_reg.h               | 109 ++-
 drivers/gpu/drm/i915/intel_device_info.c      |   4 +
 drivers/gpu/drm/i915/intel_device_info.h      |  10 +-
 drivers/gpu/drm/i915/intel_dram.c             |   6 +-
 drivers/gpu/drm/i915/intel_pch.c              |   3 +
 drivers/gpu/drm/i915/intel_pch.h              |   2 +
 drivers/gpu/drm/i915/intel_pm.c               | 120 ++-
 drivers/gpu/drm/i915/intel_step.c             |  20 +-
 drivers/gpu/drm/i915/intel_step.h             |   1 +
 drivers/gpu/drm/i915/intel_uncore.c           | 367 ++++++--
 drivers/gpu/drm/i915/intel_uncore.h           |  14 +-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 +
 include/uapi/drm/i915_drm.h                   |   3 -
 59 files changed, 3085 insertions(+), 289 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h