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[0/3] i915: Initial workarounds for Xe_HP SDV and DG2

Message ID 20211102222511.534310-1-matthew.d.roper@intel.com (mailing list archive)
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Series i915: Initial workarounds for Xe_HP SDV and DG2 | expand

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Matt Roper Nov. 2, 2021, 10:25 p.m. UTC
This is the initial batch of workarounds for these two platforms.  There
are still more workarounds to come in the future (e.g., related to other
functionality that hasn't landed yet like compute engines, multi-tile,
etc.).


Matt Roper (2):
  drm/i915/dg2: Add initial gt/ctx/engine workarounds
  drm/i915/dg2: Program recommended HW settings

Stuart Summers (1):
  drm/i915/xehpsdv: Add initial workarounds

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 392 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h             | 154 +++++++-
 drivers/gpu/drm/i915/intel_pm.c             |  31 +-
 3 files changed, 547 insertions(+), 30 deletions(-)