mbox series

[v2,0/3] i915: Upstream initial DG2 PCI IDs

Message ID 20220425211251.77154-1-matthew.d.roper@intel.com (mailing list archive)
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Series i915: Upstream initial DG2 PCI IDs | expand

Message

Matt Roper April 25, 2022, 9:12 p.m. UTC 
We've had all of our DG2 and ATS-M PCI IDs in the topic/core-for-CI
branch for a while, but we've now got the critical uapi changes in place
to unblock upstreaming the initial subset (which correspond to
"motherboard down" designs) through the drm-intel tree.  The remaining
IDs (which correspond to add-in card designs) will remain in the
topic/core-for-CI branch until some additional prerequisite
functionality lands.

Since the topic/core-for-CI branch is a rebasing branch, we'll just
rebase the relevant IDs out of it when the time comes, but I'm sending
them as a formal revert here so that the CI system doesn't get confused
when testing the series.

Note that a handful of new DG2-G12 IDs have also shown up recently, so
those additional IDs are also included here.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>

Matt Roper (3):
  topic/core-for-CI:  Revert DG2 and ATS-M device IDs
  drm/i915: Add first set of DG2 PCI IDs
  topic/core-for-CI: Add remaining DG2 and ATS-M device IDs

 include/drm/i915_pciids.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)