| Message ID | 20220428041926.1483683-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | i915: Turn on compute engine support | expand |
I did some light testing with our anvil (Vulkan) and iris (OpenGL) Mesa drivers after applying these patches on top of drm-tip tagged intel/CI_DRM_11574. All the unit tests that I tried passed. I also ran the gl_manhattan31 benchmark which used the compute engine for iris compute shader ops. Series: Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Jordan Justen <jordan.l.justen@intel.com> -Jordan On 2022-04-27 21:19:22, Matt Roper wrote: > Now that the necessary GuC-based hardware workarounds have landed, we're > finally ready to actually enable compute engines for use by userspace. > All of the "under-the-hood" heavy lifting already landed a while back in > other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE > to the uapi enum and add the CCS engines to the engine lists for the > Xe_HP SDV and DG2. > > Userspace (Mesa) is linked in the ABI patch. Existing IGT tests (e.g., > i915_hangman) provide test coverage for general engine behavior since compute > engines should follow the same general rules as other engines. We've also > recently added some additional subtests like > igt@gem_reset_stats@shared-reset-domain to cover the user-visible impacts of > the compute engines sharing the same hardware reset domain as the render > engine. > > v2: > - Update TLB invalidation register for compute engines and move it to a > separate patch since it isn't related to the new uapi. (Tvrtko, > Prathap) > - Move new kerneldoc for pre-existing engine classes to a separate > patch. (Andi) > - Drop the compute UMD merge request link for now because it also > included some additional multi-tile uapi that we're not ready to > upstream just yet. Even if they don't have a disentangled MR ready > for reference, we still have the Mesa MR as a key userspace consumer. > (Tvrtko) > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > Daniele Ceraolo Spurio (1): > drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines > > Matt Roper (3): > drm/i915/uapi: Add kerneldoc for engine class enum > drm/i915/xehp: Add register for compute engine's MMIO-based TLB > invalidation > drm/i915/xehp: Add compute engine ABI > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt.c | 1 + > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/i915_drm_client.c | 1 + > drivers/gpu/drm/i915/i915_drm_client.h | 2 +- > drivers/gpu/drm/i915/i915_pci.c | 6 +- > include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- > 7 files changed, 65 insertions(+), 10 deletions(-) > > -- > 2.35.1 >
Now that the necessary GuC-based hardware workarounds have landed, we're finally ready to actually enable compute engines for use by userspace. All of the "under-the-hood" heavy lifting already landed a while back in other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE to the uapi enum and add the CCS engines to the engine lists for the Xe_HP SDV and DG2. Userspace (Mesa) is linked in the ABI patch. Existing IGT tests (e.g., i915_hangman) provide test coverage for general engine behavior since compute engines should follow the same general rules as other engines. We've also recently added some additional subtests like igt@gem_reset_stats@shared-reset-domain to cover the user-visible impacts of the compute engines sharing the same hardware reset domain as the render engine. v2: - Update TLB invalidation register for compute engines and move it to a separate patch since it isn't related to the new uapi. (Tvrtko, Prathap) - Move new kerneldoc for pre-existing engine classes to a separate patch. (Andi) - Drop the compute UMD merge request link for now because it also included some additional multi-tile uapi that we're not ready to upstream just yet. Even if they don't have a disentangled MR ready for reference, we still have the Mesa MR as a key userspace consumer. (Tvrtko) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Daniele Ceraolo Spurio (1): drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines Matt Roper (3): drm/i915/uapi: Add kerneldoc for engine class enum drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation drm/i915/xehp: Add compute engine ABI drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/i915_drm_client.c | 1 + drivers/gpu/drm/i915/i915_drm_client.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 6 +- include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++-- 7 files changed, 65 insertions(+), 10 deletions(-)