From patchwork Wed May 11 00:57:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77ECBC433EF for ; Wed, 11 May 2022 06:30:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C26110EA5A; Wed, 11 May 2022 06:30:35 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8966810F42E; Wed, 11 May 2022 00:58:12 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="251594206" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="251594206" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:11 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="593838070" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:08 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v3 0/3] Clear TLB caches in all tiles when object is removed Date: Wed, 11 May 2022 02:57:53 +0200 Message-Id: <20220511005756.113245-1-andi.shyti@studenti.polito.it> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 11 May 2022 06:30:33 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, The real fix is in patch 2. The rest is a helper that adds the with_intel_gt_pm_if_awake() (from Chris) and one more check on the status of the engine before accessing it for clearing the TLB. Andi Changelog ========= v2 -> v3 (v2: https://patchwork.freedesktop.org/series/103835/) - Add missing header file that was causing a compmile error. - Fix wrong patch formatting. v1 -> v2 (v1: https://patchwork.freedesktop.org/series/103831/) - Add with_intel_gt_pm_if_awake() macro for gt specific wakeref. - Check if an engine is awake before invalidating its TLB. Andi Shyti (2): drm/i915/gem: Flush TLBs for all the tiles when clearing an obj drm/i915/gt: Skip TLB invalidation if the engine is not awake Chris Wilson (1): drm/i915/gt: Ignore TLB invalidations on idle engines drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++--- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++ 3 files changed, 17 insertions(+), 3 deletions(-)