From patchwork Wed Jun 22 03:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niranjana Vishwanathapura X-Patchwork-Id: 12890047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5485EC433EF for ; Wed, 22 Jun 2022 03:57:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A84D611252C; Wed, 22 Jun 2022 03:57:12 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70B6211252C; Wed, 22 Jun 2022 03:57:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655870231; x=1687406231; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=A5GBKSGw/xKp1Ew+L+nhTsDGnKMpLI9cKZUmaWi6KdU=; b=bwjhLwNhI4i8qV0CwfTMS2ehTDxOMH5XOWlkrkdBQFYkPx7arOuW+wxH W6EAbhMzz6SO4EEjspIg5v9BRIeNca+XgIZw65SDVk4aLxoBiAryBWoub gYEImw4PZM+EN8uL9yjprJQG5k5QLuDq9HjC84P4oF3ktLPlH5LhdEuM4 z0qSBK/hsKYtfDHz8pMVx94DG6Pz+zn/oBFsotb+ojmaUSSTAmSy/BqeR qJkMbX0JWvg2OO0m+ePKgwzHqGIawZq/ZGbeWoB0Qpk8MtPGuW70LahZJ Us5INlDmkY/+BkIF5Xew56RMZo+yEV0R0WRexvrZ74SeG8cabW7BB4YW+ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10385"; a="305755230" X-IronPort-AV: E=Sophos;i="5.92,211,1650956400"; d="scan'208";a="305755230" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2022 20:57:11 -0700 X-IronPort-AV: E=Sophos;i="5.92,211,1650956400"; d="scan'208";a="643960970" Received: from nvishwa1-desk.sc.intel.com ([172.25.29.76]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Jun 2022 20:57:10 -0700 From: Niranjana Vishwanathapura To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v3 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi Date: Tue, 21 Jun 2022 20:56:47 -0700 Message-Id: <20220622035650.29256-1-niranjana.vishwanathapura@intel.com> X-Mailer: git-send-email 2.21.0.rc0.32.g243a4c7e27 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, lionel.g.landwerlin@intel.com, tvrtko.ursulin@intel.com, chris.p.wilson@intel.com, thomas.hellstrom@intel.com, oak.zeng@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, daniel.vetter@intel.com, christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This is the i915 driver VM_BIND feature design RFC patch series along with the required uapi definition and description of intended use cases. v2: Reduce the scope to simple Mesa use case. Remove all compute related uapi, vm_bind/unbind queue support and only support a timeline out fence instead of an in/out timeline fence array. v3: Expand documentation on dma-resv usage, TLB flushing, execbuf3 and VM_UNBIND. Add FENCE_VALID and TLB_FLUSH flags. Signed-off-by: Niranjana Vishwanathapura Niranjana Vishwanathapura (3): drm/doc/rfc: VM_BIND feature design document drm/i915: Update i915 uapi documentation drm/doc/rfc: VM_BIND uapi definition Documentation/gpu/rfc/i915_vm_bind.h | 243 ++++++++++++++++++++++++ Documentation/gpu/rfc/i915_vm_bind.rst | 247 +++++++++++++++++++++++++ Documentation/gpu/rfc/index.rst | 4 + include/uapi/drm/i915_drm.h | 205 +++++++++++++++----- 4 files changed, 654 insertions(+), 45 deletions(-) create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst