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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:39 -0800 (PST) From: Konrad Dybcio Subject: [PATCH v2 0/6] OPP and devfreq for all Adrenos Date: Thu, 23 Feb 2023 02:47:36 +0100 Message-Id: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIALjF9mMC/x2NQQrDIBBFrxJm3QGdQBNyldCFmmkcEBVtSyHk7 hmyfJ/3eQd0bsIdluGAxj/pUrICPQYI0eWdUTZlIEOjIRrxU6oELLWisTxZS35+Thuo711n9M3 lEPWRvynpWBu/5X8H1td5XsvAkPZwAAAA To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=2510; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qfYEQNocMpdpOTn7eel7AhIAvweJRI9r+7Gb86qiMPo=; b=E56dXGGVbqioi2hquaXMAnNHLk/bie6SAc+/Kdk47Bh6BiOLpXxDSBY+nspd3UPHVOQaDR11+OLB AxaSlPj5BmPRuDXLcRyhNLVTWYqGL/H0Gs8O7ITG338sFf19M6i/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" v1 -> v2: - Move a2xx #defines to XML - Use dev_pm_opp_find_freq_floor in the common path in [2/6] - Clarify a comment in [2/6] - Move voting from a5xx to Adreno-wide [6/6] - Pick up tags v1: https://lore.kernel.org/linux-arm-msm/20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org This series is a combination of [1] and a subset of [2] and some new stuff. With it, devfreq is used on all a2xx-a6xx (including gmu and gmu-wrapper) and all clk_set_rate(core clock) calls are dropped in favour of dev_pm_opp_set_rate, which - drumroll - lets us scale the voltage domain. DT patches making use of that will be sent separately. On top of that, a5xx gets a call to enable icc scaling from the OPP tables. No SoCs implementing a2xx have icc support yet and a3/4xx SoCs have separate logic for that, which will be updated at a later time. Getting this in for 6.4 early would be appreciated, as that would allow for getting GMU wrapper GPUs up (without VDD&icc scaling they can only run at lower freqs, which is.. ehhh..) Changes: - a3xx busy: use the _1 counter as per msm-3.x instead of _0 - a6xx-series-opp: basically rewrite, ensure compat with all gens - a2/4xx busy: new patch - a5xx icc: new patch [1] https://lore.kernel.org/linux-arm-msm/20230130093809.2079314-1-konrad.dybcio@linaro.org/ [2] https://lore.kernel.org/linux-arm-msm/20230214173145.2482651-1-konrad.dybcio@linaro.org/ Signed-off-by: Konrad Dybcio --- Konrad Dybcio (6): drm/msm/a2xx: Include perf counter reg values in XML drm/msm/adreno: Use OPP for every GPU generation drm/msm/a2xx: Implement .gpu_busy drm/msm/a3xx: Implement .gpu_busy drm/msm/a4xx: Implement .gpu_busy drm/msm/adreno: Enable optional icc voting from OPP tables drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 ++ drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 24 ++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 99 ++++++++++++++---------------- drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 8 files changed, 104 insertions(+), 57 deletions(-) --- base-commit: aaf70d5ad5e2b06a8050c51e278b0c3a14fabef5 change-id: 20230223-topic-opp-01e7112b867d Best regards,