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[83.9.31.242]) by smtp.gmail.com with ESMTPSA id d9-20020ac24c89000000b004f849605be7sm1774293lfl.292.2023.06.19.09.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 09:44:22 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v3 0/6] Adreno QoL changes Date: Mon, 19 Jun 2023 18:44:20 +0200 Message-Id: <20230517-topic-a7xx_prep-v3-0-a3ce3725385b@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOWFkGQC/4WNQQ6CMBREr2K6tqZ8hFpX3sMY81taaEJa0iLBE O7uh50L43ImM+8tLNvkbWbXw8KSnXz2MVAojwdmOgyt5b6hzEBAKapC8jEO3nCU8/wckh24vEi slZGNcI7RS2O2XCcMpqNfePU9lbR0ft419wflzucxpvdunYqt/S2YCi64RFWfHVilDNx6HzDFU 0wt22AT/AEAASqtGkTQYJz4Aqzr+gGkors4BQEAAA== To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687193061; l=1497; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=fU7IOvGFZT+jtDrFsHSlPtEO+e2x+lA6EVgMfmK5BgE=; b=UBAMGsIGb0WZMAKEbrHuoXl8s1shs2X+HNxHtR5cntD9grU6aO3tDG/rzyE3s2Ad67Wy68QFc nhLhLOplWgZDaveJw0ANYhBIme+xR984zvUcx/LroWMxZSBcJ3WxeZu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This series brings some niceties in preparation for A7xx introduction. It should be fully independent of the GMU wrapper series. Signed-off-by: Konrad Dybcio --- Changes in v3: - Pull more definitions from mesa - Decode CP_PROTECT_CNTL bitfields - Rebase on next-20230619 - Link to v2: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org Changes in v2: - Drop switching to using the GMU_AO counter in timestamp - Add a definition for REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, may be subbed with a register sync after mesa MR22901 - Link to v1: https://lore.kernel.org/r/20230517-topic-a7xx_prep-v1-0-7a964f2e99c2@linaro.org --- Konrad Dybcio (6): drm/msm/a6xx: Add some missing header definitions drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL drm/msm/a6xx: Skip empty protection ranges entries drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start drm/msm/a6xx: Improve GMU force shutdown sequence drm/msm/a6xx: Fix up GMU region reservations drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +++++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++---- 3 files changed, 29 insertions(+), 8 deletions(-) --- base-commit: 47045630bc409ce6606d97b790895210dd1d517d change-id: 20230517-topic-a7xx_prep-787a69c7d0ff Best regards,