From patchwork Tue Jun 6 09:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13268763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37249C77B7A for ; Tue, 6 Jun 2023 09:17:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 419A710E313; Tue, 6 Jun 2023 09:17:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 094C510E2F0; Tue, 6 Jun 2023 09:17:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686043030; x=1717579030; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cNS8I7NHU4sX2LJ1AfhsrKwsoeI/9k6upAgnXhRdkZw=; b=m8EvGchOg/2XQ6S/jhek0VdcwS5pNHiZis47Dzg2zF9oy0pG57buq6oM opOsc5qezKcRMT5ZVYd9dERu6BB5UpnoN/JFxyR9iD3fQTKt80UkHmd+m sfWH32rby9ynGd4k6BbIWtcPAI2M+iZpnMPF4gUa/DsPsYZ2ko9m5PEnc ArGZm5zo28VMKIwd2/XWeSnqvGDk51CC+lRB/rhRsfP3SVpablMTqc21q MnI3Dg9uiyag64NwD9BEeNmjukZzzNp3CMsFy444PMeVcPucCpibLEXbD aem8zZOUWdnIN2hR/6DFNEflf4FtVOvogPAT7kS/25VcAaaSam6lfqltU Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="359929667" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208";a="359929667" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2023 02:17:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10732"; a="774044898" X-IronPort-AV: E=Sophos;i="6.00,219,1681196400"; d="scan'208";a="774044898" Received: from yuguen-mobl2.ger.corp.intel.com (HELO intel.com) ([10.252.57.68]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2023 02:17:01 -0700 From: Andi Shyti To: Tvrtko Ursulin , Fei Yang Subject: [PATCH v16 0/1] drm/i915: Allow user to set cache at BO creation Date: Tue, 6 Jun 2023 11:16:26 +0200 Message-Id: <20230606091627.462293-1-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lihao Gu , Jordan Justen , Intel GFX , DRI Devel , Carl Zhang , Andi Shyti , Chris Wilson , Matt Roper Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fei Yang This series introduce a new extension for GEM_CREATE, 1. end support for set caching ioctl [PATCH 1/2] 2. add set_pat extension for gem_create [PATCH 2/2] v2: drop one patch that was merged separately commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function") v3: rebased on https://patchwork.freedesktop.org/series/117082/ v4: fix missing unlock introduced in v3, and solve a rebase conflict v5: replace obj->cache_level with pat_set_by_user, fix i915_cache_level_str() for legacy platforms. v6: rebased on https://patchwork.freedesktop.org/series/117480/ v7: rebased on https://patchwork.freedesktop.org/series/117528/ v8: dropped the two dependent patches that has been merged separately. Add IGT link and Tested-by (MESA). v9: addressing comments (Andi) v10: acked-by and tested-by MESA v11: drop "end support for set caching ioctl" (merged) remove tools/include/uapi/drm/i915_drm.h v12: drop Bspec reference in comment. add to commit message instead v13: sent to test with igt@gem_create@create-ext-set-pat v14: sent to test with igt@gem_create@create-ext-set-pat v15: update commit message with documentation note and t-b/a-b from Media driver folks. v16: limiting the extension to GEN12+ Test-with: 20230606090801.461782-2-andi.shyti@linux.intel.com Fei Yang (1): drm/i915: Allow user to set cache at BO creation drivers/gpu/drm/i915/gem/i915_gem_create.c | 40 +++++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++ include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++ 3 files changed, 87 insertions(+)