From patchwork Sat Jul 6 01:12:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Almeida?= X-Patchwork-Id: 13725587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C8BFC38150 for ; Sat, 6 Jul 2024 01:12:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 84EDF10E0E4; Sat, 6 Jul 2024 01:12:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="Al6QKwKf"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1EDE010E0E4; Sat, 6 Jul 2024 01:12:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=AS9cAtBh3YgCXgXDU4/Q/DI5ppPuFlEliQR7lHeCIFU=; b=Al6QKwKfrxtaZ82v3rD2sW6tBY NG3wUo2e6pDDjZAB5EexFvBpT6VyEG3pJEpGkSrwmB2faRBewSkxK5yU5qurb3hMKr+ZA6o0LhJKi on/BqqCh+3BPiXOSHNoBKFmrjV1Punqk+hSq6b0/ZuHrp5/TUKMN7ej4FqKzwgRl0XI5wE2uxUHjn 2zqdjHMTtM2nT24FulDuvyQvEaVid5mR2LL4MkZWBdSbJtybHDHxlgwpIX6x1LV2YpMaisuHJbuxK HNou44h9OqMUH8MEH1C8sUyN2iIn/+DwwO8N8hjc/Z7UOBDSVEeHz6+wb2LLPyPtRgE1Ph3NVzdCH n+ZyyEyw==; Received: from [191.19.134.16] (helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1sPtyS-00BhBm-CQ; Sat, 06 Jul 2024 03:12:24 +0200 From: =?utf-8?q?Andr=C3=A9_Almeida?= To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , daniel@ffwll.ch, Daniel Stone , =?utf-8?b?J01hcmVrIE9sxaHDoWsn?= , Dave Airlie , ville.syrjala@linux.intel.com, Xaver Hugl , Joshua Ashton , =?utf-8?q?Michel_D=C3=A4nzer?= , Dmitry Baryshkov , =?utf-8?q?Andr=C3=A9_Almeid?= =?utf-8?q?a?= Subject: [PATCH v8 0/1] drm/atomic: Ease async flip restrictions Date: Fri, 5 Jul 2024 22:12:12 -0300 Message-ID: <20240706011214.380390-1-andrealmeid@igalia.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, As per my previous patchsets, the goal of this work is to find a nice way to allow amdgpu to perform async page flips in the overlay plane as well, not only on the primary one. Currently, when using the atomic uAPI, this is the only type of plane allowed to do async flips, and every driver accepts it. In my last version, I had created a static field `bool async_flip` for drm_planes. When creating new planes, drivers could tell if such plane was allowed or not to do async flips. This would be latter checked on the atomic uAPI whenever the DRM_MODE_PAGE_FLIP_ASYNC was present. However, Dmitry Baryshkov raised a valid point about getting confused with the existing atomic_async_check() code, giving that is an function to do basically what I want: to let drivers tell DRM whether a giving plane can do async flips or not. It turns out atomic_async_check() is implemented by drivers to deal with the legacy cursor update, so it's not wired with the atomic uAPI because is something that precedes such API. So my new proposal is to just reuse this same function in the atomic uAPI path. The plane restrictions defined at atomic_async_check() should work in this codepath as well. And I will be able to allow overlays planes by modifying amdgpu_dm_plane_atomic_async_check(), and anyone else have a proper place to play with async plane restrictions as well. One note is that currently we always allow async flips for primary planes, regardless of the drivers, but not every atomic_async_check() implementation allows primary planes (because they were writing targeting cursor planes anyway...). To avoid regressions, my patch only calls atomic_async_check() for non primary planes, and always allows primary ones. Thoughts? Changelog v7: https://lore.kernel.org/dri-devel/20240618030024.500532-1-andrealmeid@igalia.com/ - Complete rewrite André Almeida (2): drm/atomic: Let drivers decide which planes to async flip drm/amdgpu: Enable async flip on overlay planes .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +-- drivers/gpu/drm/drm_atomic_uapi.c | 21 ++++++++++++++----- 2 files changed, 17 insertions(+), 7 deletions(-)