From patchwork Wed Aug 14 13:47:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13763512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EDCCC52D7B for ; Wed, 14 Aug 2024 13:48:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A63B010E488; Wed, 14 Aug 2024 13:48:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TU9/4sPd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id CACC010E48E; Wed, 14 Aug 2024 13:48:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723643304; x=1755179304; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=blm7jAQoSNHeYCs7Wlv7rh0Eni/1qDlqjkgx/wsMrPg=; b=TU9/4sPdA3HQkic8Lvw1NfOLWwbBtQ1+Ky2SeVCWm3OgIvUvaUl/OVr2 tWONOTPTAcWqOy86sVkFGW3vfuGGOKIOTdJBdUQzR+LPHFPshlJ2qq2dp tbqKGXSrS3n2wDiwHckOHcOHxfKLTvieEfhw1EchY7mhEOE2hIc++B+6o 9kCjICUaGNMxGhe7bS45kKSQr1lye20EwO3AC2SyvDtf6r5xLChtgs3Fj DbMvQ6P2X2vHmnl4GeLWVmkLjWGaI5wXmLulIVemPMPCjZdTEKqbqRJ+r +BqjURjHwbpSSdYlHMd3QogPpRF3lgTqw53SugRf6rliNvXivZs2JOzRr Q==; X-CSE-ConnectionGUID: Hu4D7IF0TR6AmWPZLiNDWQ== X-CSE-MsgGUID: 3fpavCQQSxqF7nwHchzzXw== X-IronPort-AV: E=McAfee;i="6700,10204,11164"; a="32537544" X-IronPort-AV: E=Sophos;i="6.10,146,1719903600"; d="scan'208";a="32537544" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2024 06:48:24 -0700 X-CSE-ConnectionGUID: FvU1hJn1SEuVv/XTbdkt9w== X-CSE-MsgGUID: /QtCJ8vNS1KKSpQmb7MCoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,146,1719903600"; d="scan'208";a="59153915" Received: from sschumil-mobl2.ger.corp.intel.com (HELO intel.com) ([10.245.246.62]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2024 06:48:21 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Lionel Landwerlin , Chris Wilson , Nirmoy Das , Krzysztof Niemiec , Sima , Matthew Brost , Andi Shyti Subject: [PATCH v2 0/2] Allow partial memory mapping for cpu memory Date: Wed, 14 Aug 2024 15:47:46 +0200 Message-ID: <20240814134751.116439-1-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, I am resending this patch series, not to disregard the previous discussions, but to ensure it gets tested with the IGTs that Krzysztof has provided. This patch series finalizes the memory mapping fixes and improvements by enabling partial memory mapping for CPU memory as well. The concept of partial memory mapping, achieved by adding an object offset, was implicitly introduced in commit 8bdd9ef7e9b1 ("drm/i915/gem: Fix Virtual Memory mapping boundaries calculation") for GTT memory. To address a previous discussion with Sima and Matt, this feature is used by Mesa and is required across all platforms utilizing Mesa. Although Nirmoy suggested using the Fixes tag to backport this to previous kernels, I view this as a new feature rather than a fix. Lionel, please let me know if you have a different perspective and believe this should be treated as a bug fix, requiring it to be backported to stable kernels. The IGTs have been developed in collaboration with the Mesa team to replicate the exact Mesa use case[*]. Thanks Chris for the support, thanks Krzysztof for taking care of the IGT tests, thanks Nirmoy for your reviews and thanks Sima and Matt for the discussion on this series. Andi [*] https://patchwork.freedesktop.org/patch/608232/?series=137303&rev=1 Test-with: 20240814132404.18392-1-krzysztof.niemiec@intel.com Changelog: ========== v1 -> v2 - Added Nirmoy's tags. Andi Shyti (2): drm/i915/gem: Do not look for the exact address in node drm/i915/gem: Calculate object page offset for partial memory mapping drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 ++++++---- drivers/gpu/drm/i915/i915_mm.c | 12 +++++++++++- drivers/gpu/drm/i915/i915_mm.h | 3 ++- 3 files changed, 19 insertions(+), 6 deletions(-)