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Sat, 21 Sep 2024 01:17:35 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH 0/4] drm/msm/mdss: rework UBWC registers programming Date: Sat, 21 Sep 2024 11:17:28 +0300 Message-Id: <20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIABiB7mYC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDSyND3dziXN3clOJi3dKk8mRdQwNTUwvLVAPTNGNTJaCegqLUtMwKsHn RsbW1AI4EzJNfAAAA To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1666; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=FWxmz7a337bopVTKsWHeJLal3kuOKwjodrDrKroH46g=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm7oEeg8QXbKlz5YvCz4t/2udl84Z9xp0WLVCjr E0eBawUMEqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZu6BHgAKCRCLPIo+Aiko 1dKnB/9i7/Ti1b9MR9d1Q+g5lv7IhMcVt+9dwlNHrbmi/iy9XyTh/1MVVbxvteN44VxZYgkpElh icJx0jJby8V/YsrxcxsQBsDxzAbvCRl27Fawt5WCYzug44R7yjOt9V5h7sxfFjKj12IyeQVmfxO hk6+Xx+ZWDNotIFPeowgRgjuUAQpDJMHKCBfAO0xqO3+6gRxnb7GXfhDMZ/8DlumwSFGGRucnoE vPIsYP37wcOIpGh33G5ZiFP4sEbcJ7Uq+YezDOkpfvkeBWycxujNpUEhyagl7eSLdKVTfEBD1Dn KH84lfQRyxA3uNLrLiwKUtTqscI57VydcmSZJdCMtOV/fUvg X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Current way of programming of the UBWC-related registers has been inherited from vendor's drivers. The ubwc_static was supposed to contain raw data to be programmed to the hardware, but was later repurposed to define of the bits. As it can be seen by the commit 3e30296b374a ("drm/msm: fix the highest_bank_bit for sc7180") sometimes this data gets out of sync. Rework existing msm_mdss_setup_ubwc_dec_NN() functions to be closer to the actual hardware bit definitions. Drop the ubwc_static field. Unfortunately this also introduces several "unknown" bits, for which we do not document the actual purpose. Hopefully comparing this data with the more documented Adreno UBWC feature bits will provide information about the meaning of those bits. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (4): drm/msm: move MDSS registers to separate header file drm/msm/mdss: use register definitions instead of hand-coding them drm/msm/mdss: define bitfields for the UBWC_STATIC register drm/msm/mdss: reuse defined bitfields for UBWC 2.0 drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/msm_mdss.c | 86 ++++++++++++++------------ drivers/gpu/drm/msm/msm_mdss.h | 4 +- drivers/gpu/drm/msm/registers/display/mdp5.xml | 16 ----- drivers/gpu/drm/msm/registers/display/mdss.xml | 38 ++++++++++++ 5 files changed, 89 insertions(+), 56 deletions(-) --- base-commit: 32ffa5373540a8d1c06619f52d019c6cdc948bb4 change-id: 20240921-msm-mdss-ubwc-105589e05f35 Best regards,