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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:64aa7808-outbound-1.mta.getcheckrecipient.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(35042699022)(14060799003)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2024 17:05:49.8130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4090d234-9315-425b-8eaa-08dd204f636a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB10913 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patchset attempts to define a HW abstraction framework with the hopes of standardizing and simplifying the bring up of subsequent Mali GPU support. It provides abstractions to handle GPU register and register set changes, IRQ name changes, and functional changes of subsequent GPUs based on the architecture ID (comprised of arch_major, arch_minor and arch_rev), in addition to arch-based feature detection. Patch 1/4 adds 64-bit GPU register accessors with the intention of simplifying a number of HW operations throughout the driver. Patch 2/4 prepares the foundation for the HW abstraction layer by providing parsing of the GPU_ID register to compose the architecture ID. It also reduces the recurring use of MACROS throughout the driver to parse stored register values, instead only parsing them once on initialization while providing a common structure to access the parsed properties. Patch 3/4 implements the GPU specific initialization framework. Patch 4/4 provides an example of feature detection by performing cache flushes via the GPU_COMMAND register in place of the AS_COMMAND register when a feature bit ise set. Karunika Choo (4): drm/panthor: Add 64-bit register accessors drm/panthor: Add parsed gpu properties drm/panthor: Add gpu specific initialization framework drm/panthor: Use GPU_COMMAND.FLUSH_CACHES for cache maintenance drivers/gpu/drm/panthor/Makefile | 2 + drivers/gpu/drm/panthor/panthor_device.c | 23 +- drivers/gpu/drm/panthor/panthor_device.h | 32 ++- drivers/gpu/drm/panthor/panthor_fw.c | 31 ++- drivers/gpu/drm/panthor/panthor_gpu.c | 274 +++++------------------ drivers/gpu/drm/panthor/panthor_gpu.h | 1 + drivers/gpu/drm/panthor/panthor_heap.c | 6 +- drivers/gpu/drm/panthor/panthor_hw.c | 97 ++++++++ drivers/gpu/drm/panthor/panthor_hw.h | 96 ++++++++ drivers/gpu/drm/panthor/panthor_mmu.c | 118 ++++++---- drivers/gpu/drm/panthor/panthor_props.c | 151 +++++++++++++ drivers/gpu/drm/panthor/panthor_props.h | 70 ++++++ drivers/gpu/drm/panthor/panthor_regs.h | 114 +++++++--- drivers/gpu/drm/panthor/panthor_sched.c | 7 +- 14 files changed, 702 insertions(+), 320 deletions(-) create mode 100644 drivers/gpu/drm/panthor/panthor_hw.c create mode 100644 drivers/gpu/drm/panthor/panthor_hw.h create mode 100644 drivers/gpu/drm/panthor/panthor_props.c create mode 100644 drivers/gpu/drm/panthor/panthor_props.h