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[RFC,0/4] Support for Adreno X1-85 Speedbin along with new OPP levels

Message ID 20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com (mailing list archive)
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Series Support for Adreno X1-85 Speedbin along with new OPP levels | expand

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Akhil P Oommen Jan. 8, 2025, 10:42 p.m. UTC 
This series adds gpu speedbin support for Adreno X1-85 GPU along with
additional OPP levels. Because the higher OPPs require GPU ACD feature,
this series has dependency on the GPU ACD support series [1]. Also,
there is dependency on dimtry's series which fixes dword alignment in
nvmem driver [2]. We need a small fix up on top of that and that is
being discussed there. Hence, the RFC tag.

An interesting bit here is the non-contigous "hi" bit for speedbin fuse.
Otherwise, it is business as usual.

The device tree change has a dependency on the driver changes. So the
driver changes should be picked up first.

[1] https://lore.kernel.org/lkml/20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com/
[2] https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/

-Akhil

---
Akhil P Oommen (4):
      drm/msm/adreno: Add speedbin support for X1-85
      dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
      dt-bindings: nvmem: qfprom: Add X1E80100 compatible
      arm64: dts: qcom: x1e80100: Update GPU OPP table

 .../devicetree/bindings/nvmem/qcom,qfprom.yaml     |  1 +
 arch/arm64/boot/dts/qcom/x1e80100.dtsi             | 47 ++++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c          |  5 +++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c            | 15 ++++++-
 include/dt-bindings/power/qcom-rpmpd.h             |  1 +
 5 files changed, 68 insertions(+), 1 deletion(-)
---
base-commit: 5fcdd8fcd55d1da6fdf8deb78355a5c23ce94d39
change-id: 20240807-x1e-speedbin-b4-a0c304d13983
prerequisite-message-id: 20250109-gpu-acd-v4-0-08a5efaf4a23@quicinc.com
prerequisite-patch-id: 2ac56343518c3c16229262051f52e448564f2286
prerequisite-patch-id: 1c363fb7cd864279bd97ed50a02f05f72ca00a5d
prerequisite-patch-id: 059608aac5a0a1fa11ea93a8871820f054771301
prerequisite-patch-id: de12f1b879070aca3f42973b75ed04d4d835b244
prerequisite-patch-id: 421ea499b3e901030f66f697dc0a0b718d9db20e
prerequisite-patch-id: ca6d3a3c65bd17bbcd7785e4584941a438aafcb9
prerequisite-patch-id: 017b7ba9e9bfd70719b77bf741bf0afa7f20cee0
prerequisite-message-id: 20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org
prerequisite-patch-id: c1310808de89982d41261bab69c77be2e83a6339
prerequisite-patch-id: 34a5a771be148f71d66acd4417493cc752e6d3a6
prerequisite-patch-id: 30ac1f33b3dc8979f28fdfd6303595fcfce56b84
prerequisite-patch-id: 2238546441608d9f5755b4ebc1d5ea6090c6c3bb
prerequisite-patch-id: 7a260ae7850d966e8fecd3ebc5114ac157d23c87

Best regards,