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Sun, 28 Mar 2021 16:58:06 -0700 (PDT) Received: from localhost.localdomain ([156.146.58.24]) by smtp.gmail.com with ESMTPSA id y19sm12153061qky.111.2021.03.28.16.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Mar 2021 16:58:06 -0700 (PDT) From: Bhaskar Chowdhury To: dmaengine@vger.kernel.org, dri-devel@lists.freedesktop.org, hch@lst.de, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, dave.jiang@intel.com, dan.j.williams@intel.com Subject: [PATCH 26/30] dw-axi-dmac-platform.c: Few typos fixed Date: Mon, 29 Mar 2021 05:23:22 +0530 Message-Id: <01f2fed34eca736091a46dfee38381882e5dc5e9.1616971780.git.unixbhaskar@gmail.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rdunlap@infradead.org, Bhaskar Chowdhury , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" s/configurarion/configuration/ s/inerrupts/interrupts/ s/chanels/channels/ ....two different places. s/Synopsys/Synopsis/ Signed-off-by: Bhaskar Chowdhury --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.26.3 diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index d9e4ac3edb4e..ef4da10361a7 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -35,7 +35,7 @@ /* * The set of bus widths supported by the DMA controller. DW AXI DMAC supports * master data bus width up to 512 bits (for both AXI master interfaces), but - * it depends on IP block configurarion. + * it depends on IP block configuration. */ #define AXI_DMA_BUSWIDTHS \ (DMA_SLAVE_BUSWIDTH_1_BYTE | \ @@ -1056,10 +1056,10 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) u32 status, i; - /* Disable DMAC inerrupts. We'll enable them after processing chanels */ + /* Disable DMAC interrupts. We'll enable them after processing channels */ axi_dma_irq_disable(chip); - /* Poll, clear and process every chanel interrupt status */ + /* Poll, clear and process every channel interrupt status */ for (i = 0; i < dw->hdata->nr_channels; i++) { chan = &dw->chan[i]; status = axi_chan_irq_read(chan); @@ -1511,5 +1511,5 @@ static struct platform_driver dw_driver = { module_platform_driver(dw_driver); MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); +MODULE_DESCRIPTION("Synopsis DesignWare AXI DMA Controller platform driver"); MODULE_AUTHOR("Eugeniy Paltsev ");