| Message ID | 0gLrKmUEE4VjN5rdf6dUiejliU1GhjCBvH7RFMQYY@cp7-web-044.plabs.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/fourcc: add table describing AMD modifiers bit layout | expand |
On Fri, Nov 13, 2020 at 12:21 PM Simon Ser <contact@emersion.fr> wrote: > > The table describes how each bit in the u64 value is used. Explicitly > state which values a field can take if we have defines for them. Also > add a note when a field isn't always populated. > > Forcing people to update the table when changing the bit layout should > make it more obvious when there's a mistake, I hope. > > If we get to the point where the bit layout gets more complicated, it > might be worth it to split the table into multiple tables (e.g. one for > GFX8, one for GFX9+, and so on). > > Signed-off-by: Simon Ser <contact@emersion.fr> > Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> > Cc: Alex Deucher <alexdeucher@gmail.com> > Cc: Daniel Vetter <daniel@ffwll.ch> Applied. Thanks! Alex > --- > > This already contains the fix in [1]. > > [1]: https://lists.freedesktop.org/archives/amd-gfx/2020-November/056073.html > > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index ca48ed0e6bc1..253386b7bc6a 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > * > * For multi-plane formats the above surfaces get merged into one plane for > * each format plane, based on the required alignment only. > + * > + * Bits Parameter Notes > + * ----- ------------------------ --------------------------------------------- > + * > + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* > + * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* > + * 13 DCC > + * 14 DCC_RETILE > + * 15 DCC_PIPE_ALIGN > + * 16 DCC_INDEPENDENT_64B > + * 17 DCC_INDEPENDENT_128B > + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* > + * 20 DCC_CONSTANT_ENCODE > + * 23:21 PIPE_XOR_BITS Only for some chips > + * 26:24 BANK_XOR_BITS Only for some chips > + * 29:27 PACKERS Only for some chips > + * 32:30 RB Only for some chips > + * 35:33 PIPE Only for some chips > + * 55:36 - Reserved for future use, must be zero > */ > #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) > > -- > 2.29.2 > >
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index ca48ed0e6bc1..253386b7bc6a 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * * For multi-plane formats the above surfaces get merged into one plane for * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero */ #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on). Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> --- This already contains the fix in [1]. [1]: https://lists.freedesktop.org/archives/amd-gfx/2020-November/056073.html include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)