From patchwork Thu Feb 18 20:57:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 80432 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1IKxXRV020380 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 18 Feb 2010 21:00:10 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NiDRs-0002op-Rg; Thu, 18 Feb 2010 20:58:12 +0000 Received: from sfi-mx-4.v28.ch3.sourceforge.com ([172.29.28.124] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NiDRr-0002oi-L0 for dri-devel@lists.sourceforge.net; Thu, 18 Feb 2010 20:58:11 +0000 Received-SPF: pass (sfi-mx-4.v28.ch3.sourceforge.com: domain of gmail.com designates 74.125.78.150 as permitted sender) client-ip=74.125.78.150; envelope-from=zajec5@gmail.com; helo=ey-out-1920.google.com; Received: from ey-out-1920.google.com ([74.125.78.150]) by sfi-mx-4.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NiDRq-0007yw-Cw for dri-devel@lists.sourceforge.net; Thu, 18 Feb 2010 20:58:11 +0000 Received: by ey-out-1920.google.com with SMTP id 4so1817566eyg.40 for ; Thu, 18 Feb 2010 12:58:01 -0800 (PST) Received: by 10.213.52.205 with SMTP id j13mr38810ebg.75.1266526681780; Thu, 18 Feb 2010 12:58:01 -0800 (PST) Received: from localhost.localdomain (c3-107.icpnet.pl [62.21.3.107]) by mx.google.com with ESMTPS id 16sm6873006ewy.2.2010.02.18.12.58.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 18 Feb 2010 12:58:01 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: dri-devel@lists.sourceforge.net, Dave Airlie Subject: [PATCH] drm/radeon/kms: implement setting active PCIE lanes on R600+ Date: Thu, 18 Feb 2010 21:57:59 +0100 Message-Id: <1266526679-3315-1-git-send-email-zajec5@gmail.com> X-Mailer: git-send-email 1.6.4.2 MIME-Version: 1.0 X-Spam-Score: -0.9 (/) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 DKIM_VERIFIED Domain Keys Identified Mail: signature passes verification 0.0 DKIM_SIGNED Domain Keys Identified Mail: message has a signature 0.6 AWL AWL: From: address is in the auto white-list X-Headers-End: 1NiDRq-0007yw-Cw X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 18 Feb 2010 21:00:10 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 694a4c5..e06eaba 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2863,6 +2863,82 @@ restart_ih: return IRQ_HANDLED; } +void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) +{ + uint32_t link_width_cntl, mask, target_reg; + + if (rdev->flags & RADEON_IS_IGP) + return; + + if (!(rdev->flags & RADEON_IS_PCIE)) + return; + + /* FIXME check for multi GPU */ + + /* FIXME wait for idle */ + + switch (lanes) { + case 0: + mask = RADEON_PCIE_LC_LINK_WIDTH_X0; + break; + case 1: + mask = RADEON_PCIE_LC_LINK_WIDTH_X1; + break; + case 2: + mask = RADEON_PCIE_LC_LINK_WIDTH_X2; + break; + case 4: + mask = RADEON_PCIE_LC_LINK_WIDTH_X4; + break; + case 8: + mask = RADEON_PCIE_LC_LINK_WIDTH_X8; + break; + case 12: + mask = RADEON_PCIE_LC_LINK_WIDTH_X12; + break; + case 16: + default: + mask = RADEON_PCIE_LC_LINK_WIDTH_X16; + break; + } + + link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + + if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == + (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) + return; + + link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | + RADEON_PCIE_LC_RECONFIG_NOW | + R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE | + R600_PCIE_LC_SHORT_RECONFIG_EN | + R600_PCIE_LC_RENEGOTIATE_EN); + link_width_cntl |= mask; +#if 0 + /* some northbridges can renegotiate the link rather than requiring + * a complete re-config. + * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) + */ + if (northbridge can renegotiate) + link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN; + else +#endif + link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; + + WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); + WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, + (link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW)); + + /* wait for lane set to complete */ + if (rdev->family >= CHIP_RV770) + target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; + else + target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; + link_width_cntl = RREG32(target_reg); + while (link_width_cntl == 0xffffffff) + link_width_cntl = RREG32(target_reg); +} + /* * Debugfs info */ diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 4572a66..d70b80b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -601,6 +601,7 @@ bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); void r600_hpd_set_polarity(struct radeon_device *rdev, enum radeon_hpd_id hpd); extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); +void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); static struct radeon_asic r600_asic = { .init = &r600_init, @@ -627,7 +628,7 @@ static struct radeon_asic r600_asic = { .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, .get_pcie_lanes = &rv370_get_pcie_lanes, - .set_pcie_lanes = NULL, + .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = NULL, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, @@ -673,7 +674,7 @@ static struct radeon_asic rv770_asic = { .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, .get_pcie_lanes = &rv370_get_pcie_lanes, - .set_pcie_lanes = NULL, + .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 5c0dc08..2090aeb 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -317,9 +317,14 @@ # define RADEON_PCIE_LC_LINK_WIDTH_X16 6 # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 +# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) +# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) +# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) +#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c +#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */