From patchwork Mon Mar 22 18:57:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Garrett X-Patchwork-Id: 87484 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2MIwtm1025462 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 22 Mar 2010 18:59:32 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1Ntmp4-0006yi-DB; Mon, 22 Mar 2010 18:57:58 +0000 Received: from sfi-mx-3.v28.ch3.sourceforge.com ([172.29.28.123] helo=mx.sourceforge.net) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1Ntmp3-0006yc-8W for dri-devel@lists.sourceforge.net; Mon, 22 Mar 2010 18:57:57 +0000 Received-SPF: pass (sfi-mx-3.v28.ch3.sourceforge.com: domain of redhat.com designates 209.132.183.28 as permitted sender) client-ip=209.132.183.28; envelope-from=mjg@redhat.com; helo=mx1.redhat.com; Received: from mx1.redhat.com ([209.132.183.28]) by sfi-mx-3.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1Ntmp2-0008SP-8I for dri-devel@lists.sourceforge.net; Mon, 22 Mar 2010 18:57:57 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o2MIvmsl029015 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 22 Mar 2010 14:57:49 -0400 Received: from cavan.codon.org.uk (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id o2MIvlNf029360 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Mon, 22 Mar 2010 14:57:48 -0400 Received: from lan-nat-pool-bos.redhat.com ([66.187.234.200] helo=localhost.localdomain) by cavan.codon.org.uk with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Ntmos-0001yh-9c; Mon, 22 Mar 2010 18:57:46 +0000 From: Matthew Garrett To: dri-devel@lists.sourceforge.net Subject: [PATCH 2/4] radeon: perform memory reclocking in atomic context Date: Mon, 22 Mar 2010 14:57:38 -0400 Message-Id: <1269284260-12224-2-git-send-email-mjg@redhat.com> In-Reply-To: <1269284260-12224-1-git-send-email-mjg@redhat.com> References: <1269284260-12224-1-git-send-email-mjg@redhat.com> X-SA-Do-Not-Run: Yes X-SA-Exim-Connect-IP: 66.187.234.200 X-SA-Exim-Mail-From: mjg@redhat.com X-SA-Exim-Scanned: No (on cavan.codon.org.uk); SAEximRunCond expanded to false X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-Spam-Score: -0.8 (/) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 AWL AWL: From: address is in the auto white-list X-Headers-End: 1Ntmp2-0008SP-8I Cc: alexdeucher@gmail.com, Matthew Garrett X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 22 Mar 2010 18:59:32 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 9a7d16b..08e22fe 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -197,11 +197,13 @@ void r100_set_power_state(struct radeon_device *rdev) /* set memory clock */ if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) { - radeon_sync_with_vblank(rdev); - radeon_pm_debug_check_in_vbl(rdev, false); - radeon_set_memory_clock(rdev, mclk); - radeon_pm_debug_check_in_vbl(rdev, true); - rdev->pm.current_mclk = mclk; + if (!rdev->pm.active_crtcs) { + radeon_set_memory_clock(rdev, mclk); + rdev->pm.current_mclk = mclk; + } else { + rdev->pm.new_mclk = mclk; + } + radeon_sync_with_vblank(rdev); DRM_INFO("Setting: m: %d\n", mclk); } @@ -485,11 +487,25 @@ int r100_irq_process(struct radeon_device *rdev) if (status & RADEON_CRTC_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 0); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); } if (status & RADEON_CRTC2_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 1); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); } if (status & RADEON_FP_DETECT_STAT) { diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index adc558b..a89821b 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -299,11 +299,13 @@ void r600_set_power_state(struct radeon_device *rdev) /* set memory clock */ if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) { + if (!rdev->pm.active_crtcs) { + radeon_set_memory_clock(rdev, mclk); + rdev->pm.current_mclk = mclk; + } else { + rdev->pm.new_mclk = mclk; + } radeon_sync_with_vblank(rdev); - radeon_pm_debug_check_in_vbl(rdev, false); - radeon_set_memory_clock(rdev, mclk); - radeon_pm_debug_check_in_vbl(rdev, true); - rdev->pm.current_mclk = mclk; DRM_INFO("Setting: m: %d\n", mclk); } @@ -3020,6 +3022,13 @@ restart_ih: if (disp_int & LB_D1_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 0); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); disp_int &= ~LB_D1_VBLANK_INTERRUPT; DRM_DEBUG("IH: D1 vblank\n"); @@ -3042,6 +3051,13 @@ restart_ih: if (disp_int & LB_D2_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 1); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); disp_int &= ~LB_D2_VBLANK_INTERRUPT; DRM_DEBUG("IH: D2 vblank\n"); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index e8e2fe3..ac403e4 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -727,6 +727,7 @@ struct radeon_pm { int default_power_state_index; u32 current_sclk; u32 current_mclk; + u32 new_mclk; struct radeon_i2c_chan *i2c_bus; /* r6xx+ only */ u32 low_simd_mask; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 00bae31..0af81b7 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1941,7 +1941,7 @@ void radeon_atom_set_memory_clock(struct radeon_device *rdev, args.ulTargetMemoryClock = mem_clock; /* 10 khz */ - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + atom_execute_table_atomic(rdev->mode_info.atom_context, index, (uint32_t *)&args); } void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 55f00a7..83eda0e 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -484,11 +484,25 @@ int rs600_irq_process(struct radeon_device *rdev) if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 0); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); } if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 1); rdev->pm.vblank_sync = true; + if (rdev->pm.new_mclk) { + radeon_pm_debug_check_in_vbl(rdev, false); + radeon_set_memory_clock(rdev, rdev->pm.new_mclk); + radeon_pm_debug_check_in_vbl(rdev, true); + rdev->pm.current_mclk = rdev->pm.new_mclk; + rdev->pm.new_mclk = 0; + } wake_up(&rdev->irq.vblank_queue); } if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {