From patchwork Fri Mar 26 18:07:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 88548 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2QIA18o011929 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 26 Mar 2010 18:10:36 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NvDx9-0003Qe-8f; Fri, 26 Mar 2010 18:08:15 +0000 Received: from sfi-mx-1.v28.ch3.sourceforge.com ([172.29.28.121] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NvDx7-0003QS-Cg for dri-devel@lists.sourceforge.net; Fri, 26 Mar 2010 18:08:13 +0000 Received-SPF: pass (sfi-mx-1.v28.ch3.sourceforge.com: domain of virtuousgeek.org designates 67.222.54.6 as permitted sender) client-ip=67.222.54.6; envelope-from=jbarnes@virtuousgeek.org; helo=outbound-mail-313.bluehost.com; Received: from outbound-mail-313.bluehost.com ([67.222.54.6]) by sfi-mx-1.v28.ch3.sourceforge.com with smtp (Exim 4.69) id 1NvDx5-00011Y-5r for dri-devel@lists.sourceforge.net; Fri, 26 Mar 2010 18:08:13 +0000 Received: (qmail 24408 invoked by uid 0); 26 Mar 2010 18:08:05 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 26 Mar 2010 18:08:05 -0000 Received: from [75.110.194.140] (helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1NvDwx-0003Tn-79; Fri, 26 Mar 2010 12:08:03 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org, dri-devel@lists.sourceforge.net Subject: [PATCH 4/7] drm/i915: only check for enabled PIPE*STAT interrupts Date: Fri, 26 Mar 2010 11:07:18 -0700 Message-Id: <1269626841-10852-4-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1269626841-10852-1-git-send-email-jbarnes@virtuousgeek.org> References: <1269626841-10852-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 75.110.194.140 authed with jbarnes@virtuousgeek.org} X-Spam-Score: -1.0 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 DKIM_VERIFIED Domain Keys Identified Mail: signature passes verification 0.0 DKIM_SIGNED Domain Keys Identified Mail: message has a signature 0.5 AWL AWL: From: address is in the auto white-list X-Headers-End: 1NvDx5-00011Y-5r Cc: airlied@linux.ie, Jesse Barnes X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 26 Mar 2010 18:10:37 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index aba8260..abf2713 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -260,6 +260,7 @@ typedef struct drm_i915_private { /** Cached value of IMR to avoid reads in updating the bitfield */ u32 irq_mask_reg; u32 pipestat[2]; + u32 pipe_mask[2]; /** splitted irq regs for graphics and display engine on Ironlake, irq_mask_reg is still used for display irq. */ u32 gt_irq_mask_reg; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index eca0e5b..9519346 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -141,6 +141,7 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) u32 reg = i915_pipestat(pipe); dev_priv->pipestat[pipe] |= mask; + dev_priv->pipe_mask[pipe] |= (mask >> 16); /* Enable the interrupt, clear any pending status */ I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); (void) I915_READ(reg); @@ -154,6 +155,7 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) u32 reg = i915_pipestat(pipe); dev_priv->pipestat[pipe] &= ~mask; + dev_priv->pipe_mask[pipe] &= ~(mask >> 16); I915_WRITE(reg, dev_priv->pipestat[pipe]); (void) I915_READ(reg); } @@ -868,14 +870,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) /* * Clear the PIPE(A|B)STAT regs before the IIR */ - if (pipea_stats & 0x8000ffff) { + if (pipea_stats & dev_priv->pipe_mask[0]) { if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) DRM_DEBUG_DRIVER("pipe a underrun\n"); I915_WRITE(PIPEASTAT, pipea_stats); irq_received = 1; } - if (pipeb_stats & 0x8000ffff) { + if (pipeb_stats & dev_priv->pipe_mask[1]) { if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) DRM_DEBUG_DRIVER("pipe b underrun\n"); I915_WRITE(PIPEBSTAT, pipeb_stats);