diff mbox

radeon: Fix KMS CP writeback on big endian machines.

Message ID 1302185867-23067-1-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer April 7, 2011, 2:17 p.m. UTC
From: Michel Dänzer <daenzer@vmware.com>

This is necessary even with PCI(e) GART, and it makes writeback work even with
AGP on my PowerBook. Might still be unreliable with older revisions of UniNorth
and other AGP bridges though.

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
---
 drivers/gpu/drm/radeon/radeon_fence.c |    2 +-
 drivers/gpu/drm/radeon/radeon_ring.c  |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Alex Deucher April 7, 2011, 2:33 p.m. UTC | #1
2011/4/7 Michel Dänzer <michel@daenzer.net>:
> From: Michel Dänzer <daenzer@vmware.com>
>
> This is necessary even with PCI(e) GART, and it makes writeback work even with
> AGP on my PowerBook. Might still be unreliable with older revisions of UniNorth
> and other AGP bridges though.

Looks good.

Reviewed-by: Alex Deucher <alex.deucher@gmail.com>

>
> Signed-off-by: Michel Dänzer <daenzer@vmware.com>
> ---
>  drivers/gpu/drm/radeon/radeon_fence.c |    2 +-
>  drivers/gpu/drm/radeon/radeon_ring.c  |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
> index 171b0b2..2b0ee62 100644
> --- a/drivers/gpu/drm/radeon/radeon_fence.c
> +++ b/drivers/gpu/drm/radeon/radeon_fence.c
> @@ -80,7 +80,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
>                        scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
>                else
>                        scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
> -               seq = rdev->wb.wb[scratch_index/4];
> +               seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
>        } else
>                seq = RREG32(rdev->fence_drv.scratch_reg);
>        if (seq != rdev->fence_drv.last_seq) {
> diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
> index 992d99d..55ea680 100644
> --- a/drivers/gpu/drm/radeon/radeon_ring.c
> +++ b/drivers/gpu/drm/radeon/radeon_ring.c
> @@ -248,7 +248,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
>  void radeon_ring_free_size(struct radeon_device *rdev)
>  {
>        if (rdev->wb.enabled)
> -               rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4];
> +               rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
>        else {
>                if (rdev->family >= CHIP_R600)
>                        rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
> --
> 1.7.4.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 171b0b2..2b0ee62 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -80,7 +80,7 @@  static bool radeon_fence_poll_locked(struct radeon_device *rdev)
 			scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
 		else
 			scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
-		seq = rdev->wb.wb[scratch_index/4];
+		seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
 	} else
 		seq = RREG32(rdev->fence_drv.scratch_reg);
 	if (seq != rdev->fence_drv.last_seq) {
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 992d99d..55ea680 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -248,7 +248,7 @@  void radeon_ib_pool_fini(struct radeon_device *rdev)
 void radeon_ring_free_size(struct radeon_device *rdev)
 {
 	if (rdev->wb.enabled)
-		rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4];
+		rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
 	else {
 		if (rdev->family >= CHIP_R600)
 			rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);