From patchwork Fri May 20 08:34:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 802782 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4K8dl91003411 for ; Fri, 20 May 2011 08:40:08 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EFED9E988 for ; Fri, 20 May 2011 01:39:47 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qy0-f170.google.com (mail-qy0-f170.google.com [209.85.216.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 816AD9E7F2 for ; Fri, 20 May 2011 01:34:45 -0700 (PDT) Received: by qyk32 with SMTP id 32so172258qyk.15 for ; Fri, 20 May 2011 01:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=BbqLzOgH+2TsoKBPIyOPl1g/75UmsScsCB/4BJMFndQ=; b=PFJpZ5NbQd3gBOObjVvyaFieB+CwlVKeBNSQSI5RwIvPhJ+/fvSGs/7rhSltUkNOr6 u3WbnwHjW0oJoq8YYM519yEOHkIEoR6h0kIXmTkr4Va5yXJpHKrXr6idsq8x8i4SkIS3 cgmOfuVILDVmNKXt0xm4CtugQNnVF6jJW5wUM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=fGtXvWAC/K/KaeTsTpeXc2eq8Bv0K0vDeZQCCuaNhNLVVzH9qkPYOgzbMTVpaL5VKZ GTXQH3B60w2hcTAVHeWbzzPnhbVNJnaaWPjxBnKZA18oLENo7YXsL7LLfcvNRAHMjJrK 6HnLwlSSQbSCHVpeeHx8VQ4cE554JLe7SPFwg= Received: by 10.229.114.77 with SMTP id d13mr3089816qcq.219.1305880484973; Fri, 20 May 2011 01:34:44 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-7.washdc.fios.verizon.net [74.96.105.7]) by mx.google.com with ESMTPS id s9sm2112372qco.36.2011.05.20.01.34.43 (version=SSLv3 cipher=OTHER); Fri, 20 May 2011 01:34:44 -0700 (PDT) From: Alex Deucher To: airlied@gmail.com, dri-devel@lists.freedesktop.org Subject: [PATCH 04/18] drm/radeon/kms: fix up DP clock programming on DCE4/5 Date: Fri, 20 May 2011 04:34:17 -0400 Message-Id: <1305880471-1472-4-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1305880471-1472-1-git-send-email-alexdeucher@gmail.com> References: <1305880471-1472-1-git-send-email-alexdeucher@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 20 May 2011 08:40:08 +0000 (UTC) In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c | 12 ++++++++++-- drivers/gpu/drm/radeon/radeon_encoders.c | 11 ++++++++--- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index ff0d1ca..9770aff 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1443,11 +1443,19 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) uint32_t pll_in_use = 0; if (ASIC_IS_DCE4(rdev)) { - /* if crtc is driving DP and we have an ext clock, use that */ list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { if (test_encoder->crtc && (test_encoder->crtc == crtc)) { + /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, + * depending on the asic: + * DCE4: PPLL or ext clock + * DCE5: DCPLL or ext clock + * + * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip + * PPLL/DCPLL programming and only program the DP DTO for the + * crtc virtual pixel clock. + */ if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { - if (rdev->clock.dp_extclk) + if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) return ATOM_PPLL_INVALID; } } diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 6c6793e..4d66e24 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -988,11 +988,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t } if (ASIC_IS_DCE5(rdev)) { - if (is_dp && rdev->clock.dp_extclk) - args.v4.acConfig.ucRefClkSource = 3; /* external src */ - else + /* On DCE5 DCPLL usually generates the DP ref clock */ + if (is_dp) { + if (rdev->clock.dp_extclk) + args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; + else + args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; + } else args.v4.acConfig.ucRefClkSource = pll_id; } else { + /* On DCE4, if there is an external clock, it generates the DP ref clock */ if (is_dp && rdev->clock.dp_extclk) args.v3.acConfig.ucRefClkSource = 2; /* external src */ else