From patchwork Thu Sep 1 17:05:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 1119702 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p81H5YJ1026912 for ; Thu, 1 Sep 2011 17:05:56 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5A249EE99 for ; Thu, 1 Sep 2011 10:05:33 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qy0-f177.google.com (mail-qy0-f177.google.com [209.85.216.177]) by gabe.freedesktop.org (Postfix) with ESMTP id C22CC9EE99 for ; Thu, 1 Sep 2011 10:05:23 -0700 (PDT) Received: by qyk2 with SMTP id 2so1156905qyk.15 for ; Thu, 01 Sep 2011 10:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; bh=MEcjpRlZ629cJgCItGh7ZXKjxzTMB8aQzWXVOxgesdo=; b=ED3ELvXyEXkjGc/XH2jVrfQtRc/TmBvX0A9H8YiTGPqqRttNo/kM1tb+iVifyBMQn4 f//KmgliDZkCh54Ts5kwtqi9uUH8APPBSlgNROA2ap+bPCPukMs6Pcw8WeafcLRXdfev PMw/alEtPK2tE2Of/C8HH+xTQ143C0fatFQ3U= Received: by 10.52.23.198 with SMTP id o6mr81415vdf.269.1314896722929; Thu, 01 Sep 2011 10:05:22 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net [74.96.105.49]) by mx.google.com with ESMTPS id eu2sm182300vdb.21.2011.09.01.10.05.21 (version=SSLv3 cipher=OTHER); Thu, 01 Sep 2011 10:05:21 -0700 (PDT) From: alexdeucher@gmail.com To: airlied@gmail.com, dri-devel@lists.freedesktop.org Subject: [PATCH] drm/radeon/kms: make sure pci max read request size is valid on evergreen+ Date: Thu, 1 Sep 2011 13:05:15 -0400 Message-Id: <1314896715-7870-1-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.1.1 Cc: Alex Deucher , stable@kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 01 Sep 2011 17:05:56 +0000 (UTC) From: Alex Deucher If the bios or OS sets the pci max read request size to 0 or an invalid value (6,7), it can result in a hang or slowdown. Check and set it to something sane if it's invalid. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=42162 Signed-off-by: Alex Deucher Cc: stable@kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/radeon/ni.c | 3 +++ 2 files changed, 27 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index d8b725d..1e040f5 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -41,6 +41,28 @@ static void evergreen_gpu_init(struct radeon_device *rdev); void evergreen_fini(struct radeon_device *rdev); static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); +#define PCI_DEVICE_CNTL 0x60 +#define PCI_MAX_READ_REQUEST_SIZE_SHIFT 12 +#define PCI_MAX_READ_REQUEST_SIZE_MASK (7 << 12) + +void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) +{ + u16 tmp; + + pci_read_config_word(rdev->pdev, PCI_DEVICE_CNTL, &tmp); + + /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it + * to avoid hangs or perfomance issues + */ + if ((((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 0) || + (((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 6) || + (((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 7)) { + tmp &= ~PCI_MAX_READ_REQUEST_SIZE_MASK; + tmp |= (2 << PCI_MAX_READ_REQUEST_SIZE_SHIFT); + pci_write_config_word(rdev->pdev, PCI_DEVICE_CNTL, tmp); + } +} + void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) { /* enable the pflip int */ @@ -1865,6 +1887,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + evergreen_fix_pci_max_read_req_size(rdev); + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; cc_gc_shader_pipe_config |= diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index d916c82..d6cb534 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -39,6 +39,7 @@ extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); extern void evergreen_mc_program(struct radeon_device *rdev); extern void evergreen_irq_suspend(struct radeon_device *rdev); extern int evergreen_mc_init(struct radeon_device *rdev); +extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); #define EVERGREEN_PFP_UCODE_SIZE 1120 #define EVERGREEN_PM4_UCODE_SIZE 1376 @@ -724,6 +725,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + evergreen_fix_pci_max_read_req_size(rdev); + mc_shared_chmap = RREG32(MC_SHARED_CHMAP); mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);