From patchwork Tue Jul 17 18:02:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 1206471 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E6C73DF25A for ; Tue, 17 Jul 2012 18:10:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6CE29F781 for ; Tue, 17 Jul 2012 11:10:28 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-yw0-f49.google.com (mail-yw0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BDE89E779 for ; Tue, 17 Jul 2012 11:02:57 -0700 (PDT) Received: by mail-yw0-f49.google.com with SMTP id j52so746572yhj.36 for ; Tue, 17 Jul 2012 11:02:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=EyuXi95x4NoqR2Y7qosdOrfLu/h8I9sRZtT8APhBv8U=; b=T/iiDBJAIooa/cZO3ypMzA6dYZB+vmKo4rjvPWN3zLKYyoDjiP7SZGUs7NrVWmpHwU /PburUHv1BnwqrjExsMYeao4Hn0AUXuHd7tS27XsWoEMyc3g3yaPlRLebFOpmc23ESCE L8XgNP8JBev6WpGbuyDD0Jax9+MKzJB6nfBu6xp7h9fyL/QCtrf9Jahdh4NlCI3HkNO7 eGobNHDRm+H83GbI9ehfsG1PmWml/JQ+umr0Ls9XFlF5sUjz9rY9mH0VY7zg1ce85RZn 3jgxoA5zcAjUkemo5QNjHv7QlSJL2TNg7bsTOTUrZtqCfvGqCE+qGjoAjkG3sAC4jv0p FKKQ== Received: by 10.236.109.198 with SMTP id s46mr2624570yhg.118.1342548176971; Tue, 17 Jul 2012 11:02:56 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by mx.google.com with ESMTPS id w61sm35713765yhi.5.2012.07.17.11.02.55 (version=SSLv3 cipher=OTHER); Tue, 17 Jul 2012 11:02:56 -0700 (PDT) From: alexdeucher@gmail.com To: airlied@gmail.com, dri-devel@lists.freedesktop.org Subject: [PATCH 04/16] drm/radeon: add rptr save support for r1xx-r5xx Date: Tue, 17 Jul 2012 14:02:32 -0400 Message-Id: <1342548164-1948-5-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1342548164-1948-1-git-send-email-alexdeucher@gmail.com> References: <1342548164-1948-1-git-send-email-alexdeucher@gmail.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/r100.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 4ee5a74..2e0a603 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -1060,6 +1060,14 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) } ring->ready = true; radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); + + if (radeon_ring_supports_scratch_reg(rdev, ring)) { + r = radeon_scratch_get(rdev, &ring->rptr_save_reg); + if (r) { + DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); + ring->rptr_save_reg = 0; + } + } return 0; } @@ -1070,6 +1078,7 @@ void r100_cp_fini(struct radeon_device *rdev) } /* Disable ring */ r100_cp_disable(rdev); + radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); DRM_INFO("radeon: cp finalized\n"); } @@ -3661,6 +3670,12 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + if (ring->rptr_save_reg) { + u32 next_rptr = ring->wptr + 2 + 3; + radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); + radeon_ring_write(ring, next_rptr); + } + radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); radeon_ring_write(ring, ib->gpu_addr); radeon_ring_write(ring, ib->length_dw);