From patchwork Wed Jul 25 03:07:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 1234211 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id BB9C13FD4F for ; Wed, 25 Jul 2012 03:23:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 988D29EB7C for ; Tue, 24 Jul 2012 20:23:42 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by gabe.freedesktop.org (Postfix) with ESMTP id D0DFC9E7C2 for ; Tue, 24 Jul 2012 20:22:39 -0700 (PDT) Received: from [127.0.0.1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id q6P37isf022462 for ; Tue, 24 Jul 2012 22:07:46 -0500 Message-ID: <1343185664.3715.35.camel@pasglop> Subject: [PATCH 3/6] drm/cirrus: Workaround for HDR access From: Benjamin Herrenschmidt To: dri-devel@lists.freedesktop.org Date: Wed, 25 Jul 2012 13:07:44 +1000 X-Mailer: Evolution 3.2.3-0ubuntu6 Mime-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Qemu has an odd behaviour with the access to HDR (could be a qemu bug, I'm investigating separately, but it affects current qemu's so we should try to work around it). Basically the internal counter that counts the reads of the 3c6 register in order to give you access to the HDR on the 5th access is initialized in such a way that it overflows if you start doing the 4-reads sequence right after reset, and thus fails to pickup the subsequent write. We work around this by doing a write before the 4 reads, which resets the counter properly. Signed-off-by: Benjamin Herrenschmidt --- drivers/gpu/drm/cirrus/cirrus_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.h b/drivers/gpu/drm/cirrus/cirrus_drv.h index 64ea597..b5685d3 100644 --- a/drivers/gpu/drm/cirrus/cirrus_drv.h +++ b/drivers/gpu/drm/cirrus/cirrus_drv.h @@ -74,6 +74,7 @@ #define WREG_HDR(v) \ do { \ + WREG8(VGA_DAC_MASK, v); /* reset counter */ \ RREG8(VGA_DAC_MASK); \ RREG8(VGA_DAC_MASK); \ RREG8(VGA_DAC_MASK); \