From patchwork Thu Aug 9 14:38:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TWFyZWsgT2zFocOhaw==?= X-Patchwork-Id: 1301161 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id D077D3FD8C for ; Thu, 9 Aug 2012 14:40:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05A18A0E66 for ; Thu, 9 Aug 2012 07:40:47 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E7449E96F for ; Thu, 9 Aug 2012 07:38:10 -0700 (PDT) Received: by wibhq4 with SMTP id hq4so290916wib.12 for ; Thu, 09 Aug 2012 07:38:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; bh=IwItSPCxOUDtjt+To+k7JkrVV6O34alRGLCjYmNfUd8=; b=xu+QDzjYtiMfOcaH5zPDJVgT+2+Uw+u9yGvjd+oxD2qCOoKHEhk3jZaEQdmqAW9jya aQQPliG9PrbuPiGEP29SF8FgQ7UByI17EBdYMds6xX63MK8fP1di7osVng7SVzXKCeXX dawCl/16jD4cew0nROFDS06FD8YbOpTfpfxc3JnDvwUTYp8bWmuG1fnNQYz3IZ/3KGup ABI1yuzQXgT2FU2nPQaOC0+sdmdXcbCAiYokFKrklsct/fZo7okEUODEeu2QF07IfWgh 23DW1Tkj/863J9kNzECD9QPq48Wbsm87e6bEPhTBhv6TfowyDIjhNZCshlh83p8whncc BnGw== Received: by 10.216.24.85 with SMTP id w63mr12231558wew.145.1344523089253; Thu, 09 Aug 2012 07:38:09 -0700 (PDT) Received: from localhost.localdomain (static-84-242-70-218.net.upcbroadband.cz. [84.242.70.218]) by mx.google.com with ESMTPS id eu4sm2010809wib.2.2012.08.09.07.38.07 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 09 Aug 2012 07:38:08 -0700 (PDT) From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] radeon: tweak TILE_SPLIT for MSAA surfaces Date: Thu, 9 Aug 2012 16:38:00 +0200 Message-Id: <1344523080-4420-2-git-send-email-maraeo@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1344523080-4420-1-git-send-email-maraeo@gmail.com> References: <1344523080-4420-1-git-send-email-maraeo@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org --- radeon/radeon_surface.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) Reviewed-by: Jerome Glisse diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 499e994..892dca6 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -871,12 +871,37 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, return 0; } - /* set tile split to row size, optimize latter for multi-sample surface - * tile split >= 256 for render buffer surface. Also depth surface want - * smaller value for optimal performances. - */ - surf->tile_split = surf_man->hw_info.row_size; - surf->stencil_tile_split = surf_man->hw_info.row_size / 2; + /* Tweak TILE_SPLIT for performance here. */ + if (surf->nsamples > 1) { + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + switch (surf->nsamples) { + case 2: + surf->tile_split = 128; + break; + case 4: + surf->tile_split = 128; + break; + case 8: + surf->tile_split = 256; + break; + case 16: /* cayman only */ + surf->tile_split = 512; + break; + default: + fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n", + surf->nsamples, __LINE__); + return -EINVAL; + } + surf->stencil_tile_split = 64; + } else { + /* tile split must be >= 256 for colorbuffer surfaces */ + surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + } + } else { + /* set tile split to row size */ + surf->tile_split = surf_man->hw_info.row_size; + surf->stencil_tile_split = surf_man->hw_info.row_size / 2; + } /* bankw or bankh greater than 1 increase alignment requirement, not * sure if it's worth using smaller bankw & bankh to stick with 2D