diff mbox

[7/7] drm/i915: Merge FDI RX reg writes during training

Message ID 1344918891-6283-8-git-send-email-keithp@keithp.com
State New, archived
Headers show

Commit Message

Keith Packard Aug. 14, 2012, 4:34 a.m. UTC
Need to turn on the error correction when enabling training or it
might not get enabled in time.

This seems to fix the FDI-B/FDI-C link training problem.

Signed-off-by: Keith Packard <keithp@keithp.com>
---
 drivers/gpu/drm/i915/intel_display.c |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Comments

Lespiau, Damien Aug. 17, 2012, 5:14 p.m. UTC | #1
On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard <keithp@keithp.com> wrote:
> @@ -2324,6 +2324,8 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
>         }
>         I915_WRITE(reg, temp);
> +       POSTING_READ(reg);
> +       udelay(100);

The docs don't mention a delay between writing the TX and RX training
patterns, the POSTING_READ() seems like a good idea.

>         reg = FDI_RX_CTL(pipe);
>         temp = I915_READ(reg);
> @@ -2334,16 +2336,15 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>                 temp &= ~FDI_LINK_TRAIN_NONE;
>                 temp |= FDI_LINK_TRAIN_NONE;
>         }
> +       /* IVB wants error correction enabled */
> +       if (IS_IVYBRIDGE(dev))
> +               temp |= FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE;
> +
>         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
>
>         /* wait one idle pattern time */
>         POSTING_READ(reg);
>         udelay(1000);
> -
> -       /* IVB wants error correction enabled */
> -       if (IS_IVYBRIDGE(dev))
> -               I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
> -                          FDI_FE_ERRC_ENABLE);
>  }
>
>  static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 754f10f..1d24d55 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2324,6 +2324,8 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
 	}
 	I915_WRITE(reg, temp);
+	POSTING_READ(reg);
+	udelay(100);
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
@@ -2334,16 +2336,15 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_NONE;
 	}
+	/* IVB wants error correction enabled */
+	if (IS_IVYBRIDGE(dev))
+		temp |= FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE;
+
 	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
 
 	/* wait one idle pattern time */
 	POSTING_READ(reg);
 	udelay(1000);
-
-	/* IVB wants error correction enabled */
-	if (IS_IVYBRIDGE(dev))
-		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
-			   FDI_FE_ERRC_ENABLE);
 }
 
 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)