diff mbox

[1/5] drm/radeon/dce4+: don't use radeon_crtc for vblank callback

Message ID 1345066573-1492-1-git-send-email-alexdeucher@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alex Deucher Aug. 15, 2012, 9:36 p.m. UTC 
From: Alex Deucher <alexander.deucher@amd.com>

This might be called before we've allocated the radeon_crtcs

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/radeon/evergreen.c |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)

Comments

Jerome Glisse Aug. 15, 2012, 11:49 p.m. UTC | #1 
On Wed, Aug 15, 2012 at 5:36 PM,  <alexdeucher@gmail.com> wrote:
> From: Alex Deucher <alexander.deucher@amd.com>
>
> This might be called before we've allocated the radeon_crtcs
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

For the series :
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

> ---
>  drivers/gpu/drm/radeon/evergreen.c |   20 ++++++++++++++++----
>  1 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index e93b80a..0c79d9e 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -37,6 +37,16 @@
>  #define EVERGREEN_PFP_UCODE_SIZE 1120
>  #define EVERGREEN_PM4_UCODE_SIZE 1376
>
> +static const u32 crtc_offsets[6] =
> +{
> +       EVERGREEN_CRTC0_REGISTER_OFFSET,
> +       EVERGREEN_CRTC1_REGISTER_OFFSET,
> +       EVERGREEN_CRTC2_REGISTER_OFFSET,
> +       EVERGREEN_CRTC3_REGISTER_OFFSET,
> +       EVERGREEN_CRTC4_REGISTER_OFFSET,
> +       EVERGREEN_CRTC5_REGISTER_OFFSET
> +};
> +
>  static void evergreen_gpu_init(struct radeon_device *rdev);
>  void evergreen_fini(struct radeon_device *rdev);
>  void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
> @@ -109,17 +119,19 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
>   */
>  void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
>  {
> -       struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
>         int i;
>
> -       if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
> +       if (crtc >= rdev->num_crtc)
> +               return;
> +
> +       if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
>                 for (i = 0; i < rdev->usec_timeout; i++) {
> -                       if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
> +                       if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
>                                 break;
>                         udelay(1);
>                 }
>                 for (i = 0; i < rdev->usec_timeout; i++) {
> -                       if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
> +                       if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
>                                 break;
>                         udelay(1);
>                 }
> --
> 1.7.7.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e93b80a..0c79d9e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -37,6 +37,16 @@ 
 #define EVERGREEN_PFP_UCODE_SIZE 1120
 #define EVERGREEN_PM4_UCODE_SIZE 1376
 
+static const u32 crtc_offsets[6] =
+{
+	EVERGREEN_CRTC0_REGISTER_OFFSET,
+	EVERGREEN_CRTC1_REGISTER_OFFSET,
+	EVERGREEN_CRTC2_REGISTER_OFFSET,
+	EVERGREEN_CRTC3_REGISTER_OFFSET,
+	EVERGREEN_CRTC4_REGISTER_OFFSET,
+	EVERGREEN_CRTC5_REGISTER_OFFSET
+};
+
 static void evergreen_gpu_init(struct radeon_device *rdev);
 void evergreen_fini(struct radeon_device *rdev);
 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
@@ -109,17 +119,19 @@  void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  */
 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 {
-	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
 	int i;
 
-	if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
+	if (crtc >= rdev->num_crtc)
+		return;
+
+	if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 		for (i = 0; i < rdev->usec_timeout; i++) {
-			if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
+			if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 				break;
 			udelay(1);
 		}
 		for (i = 0; i < rdev->usec_timeout; i++) {
-			if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
+			if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 				break;
 			udelay(1);
 		}