From patchwork Thu Oct 4 15:18:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 1545811 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 13ED7DF238 for ; Thu, 4 Oct 2012 09:33:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F24E6A0D90 for ; Thu, 4 Oct 2012 02:33:05 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTP id 99382A0C29 for ; Thu, 4 Oct 2012 00:02:03 -0700 (PDT) Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MBC00EMEWQGIZ30@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Thu, 04 Oct 2012 16:01:33 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 51.52.03860.D443D605; Thu, 04 Oct 2012 16:01:33 +0900 (KST) X-AuditID: cbfee61b-b7f2b6d000000f14-c4-506d344d8e7c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 90.52.03860.D443D605; Thu, 04 Oct 2012 16:01:33 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MBC0040MWSZQ360@mmp2.samsung.com> for dri-devel@lists.freedesktop.org; Thu, 04 Oct 2012 16:01:33 +0900 (KST) From: Rahul Sharma To: dri-devel@lists.freedesktop.org Subject: [PATCH v1 11/14] drm: exynos: hdmi: add support for exynos5 mixer Date: Thu, 04 Oct 2012 20:48:53 +0530 Message-id: <1349363936-8531-12-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1349363936-8531-1-git-send-email-rahul.sharma@samsung.com> References: <1349363936-8531-1-git-send-email-rahul.sharma@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsWyRsSkVtfXJDfAYOEVY4srX9+zOTB63O8+ zhTAGMVlk5Kak1mWWqRvl8CV8f7jS/aCF/IVk37dZmpgnCPVxcjJISFgIrH/3jdWCFtM4sK9 9WxdjFwcQgJLGSWevTjIClP0bOYpRojEdEaJ9YvesYAkhARWM0k0PqsEsdkEdCVmH3zGCGKL CChL/J24CqyBWWARk8S/Ox/YQRLCAl4SH459YgaxWQRUJY7cmwk2iFfAQ2LbyTYmiG0KEq3L DoHVcwLFF/66wQ6xzF3iybVLjBC9AhLfJh8C6uUAqpeV2HSAGWSXhMB1Nom+yx1QV0tKHFxx g2UCo/ACRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGIFhePrfM+kdjKsaLA4xCnAwKvHw WkzKCRBiTSwrrsw9xCjBwawkwrtZMTdAiDclsbIqtSg/vqg0J7X4EKMP0CUTmaVEk/OBMZJX Em9obGJuamxqaWRkZmqKQ1hJnLfZIyVASCA9sSQ1OzW1ILUIZhwTB6dUA6POjmD77rgdjNM0 5tnO4/984tLr3LCeAqYMu+W3lV7p5ShH38p/v0oyN0/OSlpoi0J68KfwqVE9V4OPnlxmohh5 /ny3xa1J/t769Vtdj0gcqbIonrGsfYOy9vK7pQICv4Jb7okrP2yZEXM+vnVhil+WJsPajV4p MYqvr13aFxcgmDP1eWZVpRJLcUaioRZzUXEiAPV7sKxwAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e+xoK6vSW6AwdbN2hZXvr5nc2D0uN99 nCmAMaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH aKySQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMeP9x5fsBS/kKyb9us3U wDhHqouRk0NCwETi2cxTjBC2mMSFe+vZuhi5OIQEpjNKrF/0jgUkISSwmkmi8VkliM0moCsx ++AzsAYRAWWJvxNXMYI0MAssYpL4d+cDO0hCWMBL4sOxT8wgNouAqsSRezPBBvEKeEhsO9nG BLFNQaJ12SGwek6g+MJfN9ghlrlLPLl2iXECI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ +bmbGMFB/kx6B+OqBotDjAIcjEo8vBaTcgKEWBPLiitzDzFKcDArifBuVswNEOJNSaysSi3K jy8qzUktPsToA3TVRGYp0eR8YATmlcQbGpuYmxqbWppYmJhZ4hBWEudt9kgJEBJITyxJzU5N LUgtghnHxMEp1cDYW8bnVj/L9OWMh8wnHiYfZn360Yvr4rO9HDtse/9EbznMUFQuWLyDe2b+ lGmrZ4QdPS6z/dzxUKYYq96eui9LWgWusxncip1u8vGKL3NNWsQCNa+9t/dmsHffaEw6rpa4 cOr5eeEffwfv/HZkQpL1w0ANRgOb0882+GeXH5zXOtd/yaLn7useK7EUZyQaajEXFScCAEal /W6fAgAA X-CFilter-Loop: Reflected X-Mailman-Approved-At: Thu, 04 Oct 2012 00:54:10 -0700 Cc: t.stanislaws@samsung.com, l.krishna@samsung.com, joshi@samsung.com, kyungmin.park@samsung.com, fahad.k@samsung.com, rahul.sharma@samsung.com, prashanth.g@samsung.com, s.shirish@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org This patch adds support for exynos5 mixer with device tree enabled. Signed-off-by: Rahul Sharma Signed-off-by: Fahad Kunnathadi --- drivers/gpu/drm/exynos/exynos_mixer.c | 49 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/exynos/regs-mixer.h | 3 ++ 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 1677345..39d2b95 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -481,6 +481,18 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) vp_regs_dump(ctx); } +static void mixer_layer_update(struct mixer_context *ctx) +{ + struct mixer_resources *res = &ctx->mixer_res; + u32 val; + + val = mixer_reg_read(res, MXR_CFG); + + /* allow one update per vsync only */ + if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK)) + mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); +} + static void mixer_graph_buffer(struct mixer_context *ctx, int win) { struct mixer_resources *res = &ctx->mixer_res; @@ -561,6 +573,11 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) mixer_cfg_scan(ctx, win_data->mode_height); mixer_cfg_rgb_fmt(ctx, win_data->mode_height); mixer_cfg_layer(ctx, win, true); + + /* layer update mandatory for mixer 16.0.33.0 */ + if (ctx->mxr_ver == MXR_VER_16_0_33_0) + mixer_layer_update(ctx); + mixer_run(ctx); mixer_vsync_set_update(ctx, true); @@ -1065,6 +1082,11 @@ fail: return ret; } +static struct mixer_drv_data exynos5_mxr_drv_data = { + .version = MXR_VER_16_0_33_0, + .is_vp_enabled = 0, +}; + static struct mixer_drv_data exynos4_mxr_drv_data = { .version = MXR_VER_0_0_0_16, .is_vp_enabled = 1, @@ -1075,6 +1097,18 @@ static struct platform_device_id mixer_driver_types[] = { .name = "s5p-mixer", .driver_data = (unsigned long)&exynos4_mxr_drv_data, }, { + .name = "exynos5-mixer", + .driver_data = (unsigned long)&exynos5_mxr_drv_data, + }, { + /* end node */ + } +}; + +static struct of_device_id mixer_match_types[] = { + { + .compatible = "samsung,exynos5-mixer", + .data = &exynos5_mxr_drv_data, + }, { /* end node */ } }; @@ -1104,8 +1138,16 @@ static int __devinit mixer_probe(struct platform_device *pdev) mutex_init(&ctx->mixer_mutex); - drv = (struct mixer_drv_data *)platform_get_device_id( - pdev)->driver_data; + if (dev->of_node) { + const struct of_device_id *match; + match = of_match_node(of_match_ptr(mixer_match_types), + pdev->dev.of_node); + drv = match->data; + } else { + drv = (struct mixer_drv_data *) + platform_get_device_id(pdev)->driver_data; + } + ctx->dev = &pdev->dev; drm_hdmi_ctx->ctx = (void *)ctx; ctx->vp_enabled = drv->is_vp_enabled; @@ -1167,9 +1209,10 @@ static SIMPLE_DEV_PM_OPS(mixer_pm_ops, mixer_suspend, NULL); struct platform_driver mixer_driver = { .driver = { - .name = "s5p-mixer", + .name = "exynos-mixer", .owner = THIS_MODULE, .pm = &mixer_pm_ops, + .of_match_table = mixer_match_types, }, .probe = mixer_probe, .remove = __devexit_p(mixer_remove), diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index fd2f4d1..5d8dbc0 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -69,6 +69,7 @@ (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) /* bits for MXR_STATUS */ +#define MXR_STATUS_SOFT_RESET (1 << 8) #define MXR_STATUS_16_BURST (1 << 7) #define MXR_STATUS_BURST_MASK (1 << 7) #define MXR_STATUS_BIG_ENDIAN (1 << 3) @@ -77,6 +78,8 @@ #define MXR_STATUS_REG_RUN (1 << 0) /* bits for MXR_CFG */ +#define MXR_CFG_LAYER_UPDATE (1 << 31) +#define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29) #define MXR_CFG_RGB601_0_255 (0 << 9) #define MXR_CFG_RGB601_16_235 (1 << 9) #define MXR_CFG_RGB709_0_255 (2 << 9)