| Message ID | 1350346873-10289-1-git-send-email-maraeo@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Dear Marek, Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák: > The calculation led to the number 8192, which is too high. what is the reason it is limited to 4096? Hardware limitation? What are the ramifications? GPU hangs, rendering errors? > --- > radeon/radeon_surface.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c > index 66c2444..eb587d2 100644 > --- a/radeon/radeon_surface.c > +++ b/radeon/radeon_surface.c > @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, > } else { > /* tile split must be >= 256 for colorbuffer surfaces */ > surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); > + if (surf->tile_split > 4096) > + surf->tile_split = 4096; > } > } else { > /* set tile split to row size */ Thanks, Paul
On Tue, Oct 16, 2012 at 2:50 AM, Paul Menzel <paulepanter@users.sourceforge.net> wrote: > Dear Marek, > > > Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák: >> The calculation led to the number 8192, which is too high. > > what is the reason it is limited to 4096? Hardware limitation? hw limit. > > What are the ramifications? GPU hangs, rendering errors? Rendering errors. Alex > >> --- >> radeon/radeon_surface.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c >> index 66c2444..eb587d2 100644 >> --- a/radeon/radeon_surface.c >> +++ b/radeon/radeon_surface.c >> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, >> } else { >> /* tile split must be >= 256 for colorbuffer surfaces */ >> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); >> + if (surf->tile_split > 4096) >> + surf->tile_split = 4096; >> } >> } else { >> /* set tile split to row size */ > > > Thanks, > > Paul > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel >
On Mon, Oct 15, 2012 at 8:21 PM, Marek Olšák <maraeo@gmail.com> wrote: > The calculation led to the number 8192, which is too high. Looks good. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > radeon/radeon_surface.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c > index 66c2444..eb587d2 100644 > --- a/radeon/radeon_surface.c > +++ b/radeon/radeon_surface.c > @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, > } else { > /* tile split must be >= 256 for colorbuffer surfaces */ > surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); > + if (surf->tile_split > 4096) > + surf->tile_split = 4096; > } > } else { > /* set tile split to row size */ > -- > 1.7.9.5 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel
In this specific case, the eg_surface_sanity function (or something like that, I don't remember its name) returns an error. Then the cascade of perfectly working fail codepaths propagate the error to the OpenGL user as an unsupported framebuffer object setup. Marek On Tue, Oct 16, 2012 at 8:50 AM, Paul Menzel <paulepanter@users.sourceforge.net> wrote: > Dear Marek, > > > Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák: >> The calculation led to the number 8192, which is too high. > > what is the reason it is limited to 4096? Hardware limitation? > > What are the ramifications? GPU hangs, rendering errors? > >> --- >> radeon/radeon_surface.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c >> index 66c2444..eb587d2 100644 >> --- a/radeon/radeon_surface.c >> +++ b/radeon/radeon_surface.c >> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, >> } else { >> /* tile split must be >= 256 for colorbuffer surfaces */ >> surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); >> + if (surf->tile_split > 4096) >> + surf->tile_split = 4096; >> } >> } else { >> /* set tile split to row size */ > > > Thanks, > > Paul
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 66c2444..eb587d2 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, } else { /* tile split must be >= 256 for colorbuffer surfaces */ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + if (surf->tile_split > 4096) + surf->tile_split = 4096; } } else { /* set tile split to row size */