From patchwork Tue Oct 16 00:21:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TWFyZWsgT2zFocOhaw==?= X-Patchwork-Id: 1597651 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 670563FD86 for ; Tue, 16 Oct 2012 00:21:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 608F7A026A for ; Mon, 15 Oct 2012 17:21:38 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D8B29E91F for ; Mon, 15 Oct 2012 17:21:26 -0700 (PDT) Received: by mail-wi0-f169.google.com with SMTP id hq4so236033wib.0 for ; Mon, 15 Oct 2012 17:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer; bh=7w2+3Lzlxz9iAYh7WYhoWclekxBG3M2516lI+2fUBc0=; b=C5ONqVmDQbwzhYhE/hTYv6nxKhi9/fU8+TpAHypY9aDBISBLz1gxHYfSvc5V8GfegV PgA5W/atNrT18pymYXmL4JSAIY8p9OzU7DUnD1xKh48/cWIZVKNQ7tkfq90Ee7Y0hsLQ hJ5rxe8V8fvsmRmzJsj//4Y3Giwe4F3k7aV0MhARwrLWNdCQq5OAdi5kS75LkATTbDOE kJTQXI6pn/69ai2wqQfRNO1yEELg9QfH3SpxTnqHP7zT6KP3AiROqRdPVFFiW3WsKs+S gwuSDOXHF0wFOwkaP3s+7MqIgDYRrT4Obf1xQe+5+6cuZ1Ab1pNOsHYy5SKdVdrMYsLH b1VA== Received: by 10.216.207.93 with SMTP id m71mr7399678weo.201.1350346885353; Mon, 15 Oct 2012 17:21:25 -0700 (PDT) Received: from localhost.localdomain (static-84-242-70-218.net.upcbroadband.cz. [84.242.70.218]) by mx.google.com with ESMTPS id cl8sm16486174wib.10.2012.10.15.17.21.21 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 17:21:22 -0700 (PDT) From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= To: dri-devel@lists.freedesktop.org Subject: [PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA Date: Tue, 16 Oct 2012 02:21:13 +0200 Message-Id: <1350346873-10289-1-git-send-email-maraeo@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher --- radeon/radeon_surface.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 66c2444..eb587d2 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, } else { /* tile split must be >= 256 for colorbuffer surfaces */ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + if (surf->tile_split > 4096) + surf->tile_split = 4096; } } else { /* set tile split to row size */